Datasheet

• LRXOK: LIN response received
• LTXOK: LIN response transmitted
• LERR: LIN Error(s)
The wake-up management can be automated using the UART wake-up capability and a node sending a
minimum of five low bits (0xF0) for LIN 2.1 and 8 low bits (0x80) for LIN 1.3. Pin change interrupt on LIN
wake-up signal can be also used to exit the device of one of its sleep modes.
Extended frame identifiers 62 (0x3E) and 63 (0x3F) are reserved to allow the embedding of user-defined
message formats and future LIN formats. The byte transfer mode offered by the UART will ensure the
upwards compatibility of LIN slaves with accommodation of the LIN protocol.
21.4.2. UART overview
The LIN/UART controller can also function as a conventional UART. By default, the UART operates as a
full duplex controller. It has local loop back circuitry for test purposes. The UART has the ability to buffer
one character for transmit and two for receive. The receive buffer is made of one 8-bit serial register
followed by one 8-bit independent buffer register. Automatic flag management is implemented when the
application puts or gets characters, thus reducing the software overhead. Because transmit and receive
services are independent, the user can save one device pin when one of the two services is not used.
The UART has an enhanced baud rate generator providing a maximum error of 2% whatever the clock
frequency and the targeted baud rate.
21.4.3. LIN/UART controller structure
Figure 21-4. LIN/UART controller block diagram.
BUFFER
FSM
RX
Get byte
Frame time-out
Synchronization
Monitoring
RxD
TX
Put byte
Finite State Machine
TxD
BAUD_RATE
Prescaler
Sample/bit
CLK
IO
Data FIFO
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
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