Datasheet

20.11.10. CAN Bit Timing Register 3
Name: CANBT3
Offset: 0xE4
Reset: 0x0
Property: R/W
Bit 7 6 5 4 3 2 1 0
PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP
Access
Reset 0 0 0 0 0 0 0
Bits 4, 5, 6 – PHS2n: Phase Segment 2
This phase is used to compensate for phase edge errors. This segment may be shortened by the re-
synchronization jump width. PHS2[2:0] shall be ≥1 and ≤PHS1[2..0]

phs2
= 
scl
× PHS2[2:0]+1
Bits 1, 2, 3 – PHS1n: Phase Segment 1
This phase is used to compensate for phase edge errors. This segment may be lengthened by the re-
synchronization jump width.

phs1
= 
scl
× PHS1[2:0]+1
Bit 0 – SMP: Sample Point(s)
This option allows to filter possible noise on TxCAN input pin.
‘SMP=1’ configuration is not compatible with ‘BRP[5:0]=0’ because TQ = Tclk
IO
. If BRP = 0, SMP must be
cleared.
Value Description
0 The sampling will occur once at the user configured sampling point - SP
1 With three-point sampling configuration the first sampling will occur two Tclk
IO
clocks before
the user configured sampling point - SP, again at one Tclk
IO
clock before SP and finally at
SP. Then the bit level will be determined by a majority vote of the three samples
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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