Datasheet

20.11.8. CAN Bit Timing Register 1
Name: CANBT1
Offset: 0xE2
Reset: 0x0
Property: R/W
Bit 7 6 5 4 3 2 1 0
BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Access
Reset 0 0 0 0 0 0
Bits 1, 2, 3, 4, 5, 6 – BRPn: Baud Rate Prescaler
The period of the CAN controller system clock Tscl is programmable and determines the individual bit
timing.

SCL
=
BRP[5:0]+1
clk
IO
frequency
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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