Datasheet

18.16.11. PSC Interrupt Flag Register
Name: PIFR
Offset: 0xBC
Reset: 0x0
Property: R/W
Bit 7 6 5 4 3 2 1 0
PEV2 PEV1 PEV PEOP
Access
Reset 0 0 0 0
Bit 3 – PEV2: PSC External Event 2 Interrupt
This bit is set by hardware when an external event which can generates a fault on module 2 occurs. Must
be cleared by software by writing a one to its location. This bit can be read even if the corresponding
interrupt is not enabled (PEVE2 bit = 0).
Bit 2 – PEV1: PSC External Event 1 Interrupt
This bit is set by hardware when an external event which can generates a fault on module 1 occurs. Must
be cleared by software by writing a one to its location. This bit can be read even if the corresponding
interrupt is not enabled (PEVE1 bit = 0).
Bit 1 – PEV: PSC External Event 0 Interrupt
This bit is set by hardware when an external event which can generates a fault on module 0 occurs. Must
be cleared by software by writing a one to its location. This bit can be read even if the corresponding
interrupt is not enabled (PEVE0 bit = 0).
Bit 0 – PEOP: PSC End Of Cycle Interrupt
This bit is set by hardware when an “end of PSC cycle” occurs. Must be cleared by software by writing a
one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEOPE bit =
0).
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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