Datasheet

18.16.10. PSC Interrupt Mask Register
Name: PIM
Offset: 0xBB
Reset: 0x0
Property: R/W
Bit 7 6 5 4 3 2 1 0
PEVE2 PEVE1 PEVE PEOPE
Access
Reset 0 0 0 0
Bit 3 – PEVE2: PSC External Event 2 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 2 generates also an
interrupt.
Bit 2 – PEVE1: PSC External Event 1 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 1 generates also an
interrupt.
Bit 1 – PEVE: PSC External Event 0 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 0 generates also an
interrupt.
Bit 0 – PEOPE: PSC End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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