Datasheet

18.16.8. PSC Control Register
Name: PCTL
Offset: 0xB7
Reset: 0x0
Property: R/W
Bit 7 6 5 4 3 2 1 0
PPRE[1:0] PCLKSEL PCCYC PRUN
Access
Reset 0 0 0 0 0
Bits 7:6 – PPRE[1:0]: PSC Prescaler Select
These two bits select the PSC input clock division factor. All generated waveforms will be modified by this
factor.
Value Description
00 No divider on PSC input clock
01 Divide the PSC input clock by 4
10 Divide the PSC input clock by 32
11 Divide the PSC clock by 256
Bit 5 – PCLKSEL: PSC Input Clock Select
This bit is used to select between CLK
PLL
or CLK
IO
clocks.
Value Description
1 Set this bit to select the fast clock input (CLK
PLL
).
0 Clear this bit to select the slow clock input (CLK
IO
).
Bit 1 – PCCYC: PSC Complete Cycle
When this bit is set, the PSC completes the entire waveform cycle before halt operation requested by
clearing PRUN.
Bit 0 – PRUN: PSC Run
Writing this bit to one starts the PSC.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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