Datasheet

18.16.7. PSC Configuration Register
Name: PCNF
Offset: 0xB5
Reset: 0x0
Property: R/W
Bit 7 6 5 4 3 2 1 0
PULOCK PMODE POPB POPA
Access
Reset 0 0 0 0
Bit 5 – PULOCK: PSC Update Lock
When this bit is set, the Output Compare Registers POCRnRA, POCRnSA, POCRnSB, POCR_RB and
the PSC Output Configuration Registers POC can be written without disturbing the PSC cycles. The
update of the PSC internal registers will be done if the PULOCK bit is released to zero.
Bit 4 – PMODE: PSC Mode
Select the mode of PSC.
Value Description
0 One Ramp mode (edge aligned)
1 Center Aligned mode
Bit 3 – POPB: PSC B Output Polarity
Value Description
0 PSC outputs B are active Low.
1 PSC outputs B are active High.
Bit 2 – POPA: PSC A Output Polarity
Value Description
0 PSC outputs A are active Low.
1 PSC outputs A are active High.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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