Datasheet

PSCn input acts indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1.
18.11. PSC Input Mode 11xb: Halt PSC and wait for software action
Figure 18-14. PSC behavior versus PSCn Input A in fault mode 11xb
PS COUTnA
P
SCOUTnB
DT0
OT0
DT1 OT1
DT0 OT0 DT0 OT0
DT1 OT1
Softwa re action (1)
P
SCn input
Note: Software action is the setting of the PRUNn bit in PCTLn register.
Used in fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-
Time1/Dead-Time1.
18.12. Analog synchronization
Each PSC module generates a signal to synchronize the ADC sample and hold; synchronisation is
mandatory for measurements.
This signal can be selected between all falling or rising edge of PSCOUTnA or PSCOUTnB outputs.
In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchronization of the
ADC. It this case, it’s minimum value is 1.
18.13. Interrupt handling
As each PSC module can be dedicated for one function, each PSC has its own interrupt system.
List of interrupt sources:
• Counter reload (end of On Time 1)
• PSC Input event (active edge or at the beginning of level configured event)
• PSC Mutual Synchronization Error
18.14. PSC clock sources
Each PSC has two clock inputs:
• CLK PLL from the PLL
• CLK I/O
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
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