Datasheet

18.9.1.2. Signal polarity
One can select the active edge (edge modes) or the active level (level modes). See PELEVnx bit
description in Section "PMICn – PSC Module n Input Control Register", page 144.
If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or the active level is
high (level modes) and vice versa for unset/falling/low.
- In 2- or 4-ramp mode, PSCn Input A is taken into account only during Dead-Time0 and On-Time0 period
(respectively Dead-Time1 and On-Time1 for PSCn Input B)
- In 1-ramp-mode PSC Input A or PSC Input B act on the whole ramp
18.9.1.3. Input mode operation
Thanks to four configuration bits (PRFM3:0), it is possible to define the mode of the PSC inputs.
Table 18-5. PSC Input mode operation.
PRFMn2:0 Description
000b No action, PSC Input is ignored
001b Disactivate module n Outputs A
010b Disactivate module n Output B
011b Disactivate module n Output A & B
10x Disactivate all PSC Output
11xb Halt PSC and Wait for Software Action
Note: All following examples are given with rising edge or high level active inputs.
18.10. PSC input modes 001b to 10xb: Deactivate outputs without changing timing
Figure 18-12. PSC behavior versus PSCn input in mode 001b to 10xb
PS COUTnA
P
SCOUTnB
P
SCn input
DT0
OT0 DT1 OT1 DT0 OT0 DT1 OT1DT0 OT0 DT1 OT1
Figure 18-13. PSC behavior versus PSCn Input A or Input B in fault mode 4
PS COUTnA
P
SCOUTnB
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1DT0 OT0 DT1 OT1
PS Cn input
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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