Datasheet

Figure 18-10. PSC input module.
Ana log
Comp
arator
n o
utput
P
SCINn
Digital
filter
PISELnA
(PI
SELnB)
PFLTEnA
(PFLTEnB)
PAOCnA
(PAOCnB)
Inp
ut
proce
ssing
(retrigge ring ...)
MPSC core
(counte r,
w
ave form
ge ne ra tor, ...)
Control
of the
six outputs
1
0
0
1
PSCOUTnA
P
SCOUTnB
CLK
PSC
CLK
PSC
CLK
PSC
PELEVnA /
(PELEVnB)
PRFMnA3:0
(PRFMnB
3:0)
PCAEnA
(PCAEnB)
2
4
18.9.1. PSC input configuration
The PSC input configuration is done by programming bits in configuration registers.
18.9.1.1. Filter enable
If the “Filter Enable” bit is set, a digital filter of four cycles is inserted before evaluation of the signal. The
disable of this function is mainly needed for prescaled PSC clock sources, where the noise cancellation
gives too high latency.
Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSC clock to
deactivate the outputs (emergency protection of external component). Likewise when used as fault input,
PSC Module n Input A or Input B have to go through PSC to act on PSCOUTn0/1/2 outputs. This way
needs that CLK
PSC
is running. So thanks to PSC Asynchronous Output Control bit (PAOCnA/B), PSCINn
input can desactivate directly the PSC outputs. Notice that in this case, input is still taken into account as
usually by Input Module System as soon as CLK
PSC
is running.
Figure 18-11. PSC input filtering.
Digital
filter
4 x CLK
PSC input
mod
ule X
O
uput
sta ge
P
SCOUTnX
PIN
P
SC Module n input
CLK
PS C
P
SC
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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