Datasheet

18.6. Update of values
To avoid asynchronous and incoherent values in a cycle, if an update of one of several values is
necessary, all values are updated at the same time at the end of the cycle by the PSC. The new set of
values is calculated by software and the update is initiated by software.
Figure 18-8. Update at the end of complete PSC cycle.
Software
P
SC
Re gulation loop
c
alcula tion
Writting in
P
SC registers
Cycle
with
se t i
Cycle
with s e t i
Cycle
with s e t i
Cycle
with s e t i
Cycle
with
se t j
End of cycle
Re que s t for
an upda te
The software can stop the cycle before the end to update the values and restart a new PSC cycle.
18.6.1. Value update synchronization
New timing values or PSC output configuration can be written during the PSC cycle. Thanks to the LOCK
configuration bit, the new whole set of values can be taken into account after the end of the PSC cycle.
When LOCK configuration bit is set, there is no update. The update of the PSC internal registers will be
done at the end of the PSC cycle if the LOCK bit is released to zero.
The registers which update is synchronized thanks to LOCK are POC, POCR0SA, POCR1SA,
POCR2SA, POCR0RA, POCR1RA, POCR2RA, POCR0SB, POCR1SB, POCR2SB and POCR_RB.
18.7. Overlap Protection
Thanks to Overlap Protection two outputs on a same module cannot be active at the same time. So it
cannot generate cross conduction. This feature can be disactivated thanks to POVEn (PSC Overlap
Enable).
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
192