Datasheet

18.4. PSC description
Figure 18-1. Power Stage Controller block diagram.
DATABUS
POCR_RB
=
PSC Counter
Waveform
generator B
PSCOUT0B
PCTLn PFRCnA
PSOCn
(Analog Comparator 1 output)
PCNFn PFRCnB
PSCIN1
PISEL1
PS C Input 1
POCR0SB
=
POCR0RA
=
POCR0SA
=
Waveform
generator A
PSCOUT0A
Waveform
generator B
PSCOUT1B
POCR1SB
=
POCR1RA
=
POCR1SA
=
Waveform
generator A
PSCOUT1A
Waveform
generator B
PSCOUT2B
POCR2SB
=
POCR2RA
=
POCR2SA
=
Waveform
generator A
PSCOUT2A
module 0
module 1
module 2
Overlap
protection
Overlap
protection
Overlap
protection
(Analog Comparator 0 output)
PSCIN0
PISEL0
PS C Input 0
(Analog Comparator 2 output)
PSCIN2
PISEL2
PS C Input 2
AC0O
AC1O
AC2O
Pre s ca le r
CLK IO
CLK PLL
The PSC is based on the use of a free-running 12-bit counter (PSC counter). This counter is able to count
up to a top value determined by the contents of POCR_RB register and then according to the selected
running mode, count down or reset to zero for another cycle.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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