Datasheet

17.4.1. General Timer/Counter Control Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: GTCCR
Offset: 0x43
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x23
Bit 7 6 5 4 3 2 1 0
TSM ICPSEL1 PSRSYNC
Access
R/W R/W R/W
Reset 0 0 0
Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value
that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler
reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be
configured to the same value without the risk of one of them advancing during configuration. When the
TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/
Counters start counting simultaneously.
Bit 6 – ICPSEL1: Timer 1 Input Capture selection
Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PC3).
Value Description
0 Select ICP1A as trigger for timer 1 input capture
1 Select ICP1B as trigger for timer 1 input capture
Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter 0, 1 prescaler will be Reset. This bit is normally cleared immediately
by hardware, except if the TSM bit is set. Note that Timer/Counter 0, 1 share the same prescaler and a
reset of this prescaler will affect the mentioned timers.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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