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16.14.9. TC1 Interrupt Flag Register

When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

Name: TIFR1

Offset: 0x36

Reset: 0x00

Property:

When addressing as I/O Register: address offset is 0x16

Bit 7 6 5 4 3 2 1 0

ICF OCFB OCFA TOV

Access

R/W R/W R/W R/W

Reset 0 0 0 0

Bit 5 – ICF: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is

set by the WGM1[3:0] to be used as the TOP value, the ICF Flag is set when the counter reaches the

TOP value.

ICF is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF can

be cleared by writing a logic one to its bit location.

Bit 2 – OCFB: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare

Note that a Forced Output Compare (FOCB) strobe will not set the OCF1B Flag.

OCFB is automatically cleared when the Output Compare Match B Interrupt Vector is executed.

Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

Bit 1 – OCFA: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare

Note that a Forced Output Compare (FOCA) strobe will not set the OCF1A Flag.

OCFA is automatically cleared when the Output Compare Match A Interrupt Vector is executed.

Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

Bit 0 – TOV: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGM1[3:0] bits setting. In Normal and CTC modes, the TOV1

Flag is set when the timer overflows. Refer to the Waveform Generation Mode bit description for the TOV

Flag behavior when using another WGM1[3:0] bit setting.

TOV1 is automatically cleared when the Timer/Counter 1 Overflow Interrupt Vector is executed.

Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

Atmel ATmega16M1/32M1/64M1 [DATASHEET]

Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016

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