Datasheet

16.14.3. TC1 Control Register C
Name: TCCR1C
Offset: 0x82
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
FOC1A FOC1B
Access
R/W R/W
Reset 0 0
Bit 7 – FOC1A: Force Output Compare for Channel A
Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM mode. When
writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform
Generation unit. The OC1A/OC1B output is changed according to its COM1x[1:0] bits setting. Note that
the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x[1:0]
bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero.
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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