Datasheet

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161

162

163

164

165

166

167

168

169

170

Note:

• The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and

the “x” indicates Output Compare unit (A/B).

• N represents the prescale divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating a PWM waveform

output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be

continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For

inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value

(WGM1[3:0]=0x9) and COM1A[1:0]=0x1, the OC1A output will toggle with a 50% duty cycle.

16.13. Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

) is therefore shown as a clock

enable signal in the following figures. The figures include information on when Interrupt Flags are set, and

when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double

buffering). The first figure shows a timing diagram for the setting of OCF1x.

Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling

clk

(clk

I/O

/1)

OCFnx

clk

I/O

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and

the “x” indicates Output Compare unit (A/B).

The next figure shows the same timing data, but with the prescaler enabled.

Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f

clk_I/O

/8)