Datasheet

diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT1
slopes mark compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a
compare match occurs.
Figure 16-8. Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx[1:0]] = 0x2)
(COMnx[1:0] = 0x3)
Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and
the “x” indicates Output Compare unit (A/B).
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either
OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same
timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The
Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM
value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the
value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a
compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP
values, the unused bits are masked to zero when any of the OCR1x registers is written. As illustrated by
the third period in the timing diagram, changing the TOP actively while the Timer/Counter is running in the
phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of
update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends
at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the
length of the rising slope is determined by the new TOP value. When these two values differ the two
slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the
output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when
changing the TOP value while the Timer/Counter is running. When using a static TOP value, there are
practically no differences between the two modes of operation.
In Phase Correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
Writing COM1x[1:0] bits to 0x2 will produce a non-inverted PWM. An inverted PWM output can be
generated by writing the COM1x[1:0] to 0x3. The actual OC1x value will only be visible on the port pin if
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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