Datasheet

rectification, and DAC applications. High frequency allows physically small sized external components
(coils, capacitors), and therefore reduces total system cost.
In Fast PWM mode, the counter is incremented until the counter value matches the TOP value. The
counter is then cleared at the following timer clock cycle. The timing diagram for the Fast PWM mode is
shown below. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-
slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal lines
on the TCNT0 slopes mark compare matches between OCR0x and TCNT0.
Figure 15-6. Fast PWM Mode, Timing Diagram
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1
Period
2 3
OCnx
OCnx
(COMnx[1:0] = 0x2)
(COMnx[1:0] = 0x3)
OCRnx Interrupt Flag Set
4 5 6 7
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is
enabled, the interrupt handler routine can be used for updating the compare value.
In Fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Writing
the TCCR0A.COM0x[1:0] bits to 0x2 will produce a non-inverted PWM; TCCR0A.COM0x[1:0]=0x3 will
produce an inverted PWM output. Writing the TCCR0A.COM0A[1:0] bits to 0x1 allows the OC0A pin to
toggle on Compare Matches if the TCCRnB.WGMn2 bit is set. This option is not available for the OC0B
pin. The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as
output. The PWM waveform is generated by setting (or clearing) the OC0x Register at the compare
match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle
the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:

OCnxPWM
=

clk_I/O
  256
N represents the prescale divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A register represents special cases for PWM waveform output in the
Fast PWM mode: If OCR0A is written equal to BOTTOM, the output will be a narrow spike for each MAX
+1 timer clock cycle. Writing OCR0A=MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM0A[1:0] bits.)
A frequency waveform output with 50% duty cycle can be achieved in Fast PWM mode by selecting
OC0x to toggle its logical level on each compare match (COM0x[1:0]=0x1). The waveform generated will
Atmel ATmega16M1/32M1/64M1 [DATASHEET]
Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016
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