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8-bit AVR Microcontroller

ATmega16M1/32M1/64M1

DATASHEET COMPLETE

Introduction

The Atmel

ATmega16M1/32M1/64M1 is a low-power CMOS 8-bit

microcontroller based on the AVR

enhanced RISC architecture. By

executing powerful instructions in a single clock cycle, the

ATmega16M1/32M1/64M1 achieves throughputs close to 1 MIPS per MHz.

This empowers system designer to optimize the device for power

consumption versus processing speed.

Features

• High performance, low power 8-bit AVR

microcontroller

• Advanced RISC architecture

– 131 powerful instructions - most single clock cycle execution

– 32 × 8 general purpose working registers

– Fully static operation

– Up to 1 MIPS throughput per MHz

– On-chip 2-cycle multiplier

• Data and non-volatile program memory

– 16/32/64KBytes flash of in-system programmable program

memory

– 512B/1K/2KBytes of in-system programmable EEPROM

– 1/2/4KBytes internal SRAM

– Write/erase cycles: 10,000 flash/ 100,000 EEPROM

– Data retention: 20 years at 85°C/ 100 years at 25°C

(1)

– Optional boot code section with independent lock bits

• In-system programming by on-chip boot program

• True read-while-write operation

– Programming lock for flash program and EEPROM data security

• On-chip debug interface (debugWIRE)

• CAN 2.0A/B with six message objects - ISO 16845 certified

• LIN 2.1 and 1.3 controller or 8-bit UART

• One 12-bit high speed PSC (power stage controller)

– Non overlapping inverted PWM output pins with flexible dead-

time

Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016

Summary of content (429 pages)

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8-bit AVR Microcontroller ATmega16M1/32M1/64M1 DATASHEET COMPLETE Introduction ® The Atmel ATmega16M1/32M1/64M1 is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16M1/32M1/64M1 achieves throughputs close to 1 MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed.
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• – Variable PWM duty cycle and frequency – Synchronous update of all PWM registers – Auto stop function for emergency event Peripheral features – One 8-bit general purpose timer/counter with separate prescaler, compare mode and capture mode – One 16-bit general purpose timer/counter with separate prescaler, compare mode and capture mode – One master/slave SPI serial interface – • • • • 10-bit ADC • Up to 11 single ended channels and three fully differential ADC channel pairs • Programmable gain (5×, 10
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Table of Contents Introduction......................................................................................................................1 Features.......................................................................................................................... 1 1. Pin configurations...................................................................................................... 9 1.1. Pin descriptions.................................................................................
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9.6. PLL............................................................................................................................................. 52 9.7. 9.8. 9.9. 9.10. 9.11. 128kHz Internal Oscillator.......................................................................................................... 53 External Clock............................................................................................................................ 53 Clock Output Buffer................................
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15.7. Modes of Operation..................................................................................................................132 15.8. Timer/Counter Timing Diagrams...............................................................................................136 15.9. Register Description................................................................................................................. 138 16. TC1 - 16-bit Timer/Counter1 with PWM...................................................
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19.5. Register Description................................................................................................................. 217 20. CAN – Controller Area Network.............................................................................224 20.1. Features................................................................................................................................... 224 20.2. Overview.........................................................................................
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25.2. Overview...................................................................................................................................348 25.3. Operation..................................................................................................................................349 25.4. Starting a conversion................................................................................................................350 25.5. Register Description.............................................
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30.2. Pin driver strength.................................................................................................................... 407 30.3. 30.4. 30.5. 30.6. Pin Thresholds and Hysteresis.................................................................................................408 BOD Thresholds and Analog Comparator Hysteresis.............................................................. 411 Internal Oscillator Speed........................................................................
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Pin configurations P D0 (P CINT16/P S COUT0A) P B7 (ADC4/P S COUT0B/S CK/P CINT7) P B6 (ADC7/P S COUT1B/P CINT6) P B5 (ADC6/INT2/ACMP N1/AMP 2-/P CINT5) P C7 (D2A/AMP 2+/P CINT15) P C0 (P CINT8/INT3/P S COUT1A) P D1 (P CINT17/P S CIN0/CLKO) 32 31 30 29 28 27 26 25 P E0 (P CINT24/RES ET/OCD) Figure 1-1. Atmel ATmega16M1/32M1/64M1 TQFP32/QFN32 (7mm × 7mm) package.
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1.1. Pin descriptions Table 1-1. Pinout description. QFN32 pin number Mnemonic Type Name, function, and alternate function 5 GND Power Ground: 0V reference 20 AGND Power Analog ground: 0V reference for analog part 4 VCC Power Power supply 19 AVCC Power Analog power supply: This is the power supply voltage for analog part For a normal use this pin must be connected 21 AREF Power Analog reference: reference for analog converter . This is the reference voltage of the A/D converter.
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QFN32 pin number Mnemonic Type Name, function, and alternate function 28 PB7 ADC4 (Analog Input Channel 4) PSCOUT0B (1) (PSC Module 0 Output B) I/O SCK (SPI Clock) PCINT7 (Pin Change Interrupt 7) 30 PC0 I/O PSCOUT1A (1) (PSC Module 1 Output A) INT3 (External Interrupt 3 Input) PCINT8 (Pin Change Interrupt 8) 3 PC1 I/O PSCIN1 (PSC Digital Input 1) OC1B (Timer 1 Output Compare B) SS_A (Alternate SPI Slave Select) PCINT9 (Pin Change Interrupt 9) 6 PC2 I/O T0 (Timer 0 clock input) TXCAN (CAN T
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QFN32 pin number Mnemonic Type Name, function, and alternate function 32 PD1 PSCIN0 (PSC Digital Input 0) CLKO (System Clock Output) I/O PCINT17 (Pin Change Interrupt 17) 1 PD2 I/O OC1A (Timer 1 Output Compare A) PSCIN2 (PSC Digital Input 2) MISO_A (Programming & alternate SPI Master In Slave Out) PCINT18 (Pin Change Interrupt 18) 2 PD3 I/O TXD (UART Tx data) TXLIN (LIN Transmit Output) OC0A (Timer 0 Output Compare A) SS (SPI Slave Select) MOSI_A (Programming & alternate Master Out SPI Slave I
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QFN32 pin number Mnemonic Type Name, function, and alternate function 10 PE1 XTAL1 (XTAL Input) OC0B (Timer 0 Output Compare B) I/O PCINT25 (Pin Change Interrupt 25) 11 PE2 I/O XTAL2 (XTAL Output) ADC0 (Analog Input Channel 0) PCINT26 (Pin Change Interrupt 26) 1. 2. Note: Only for Atmel Atmega32M1/64M1. Note: On the engineering samples, the ACMPN3 alternate function is not located on PC4. It is located on PE2.
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2. Ordering Information 2.1. ATmega16M1 Speed [MHz] Power Supply [V] Ordering Code Package Operational Range 16 2.7 - 5.5 ATmega16M1-AU ATmega16M1-MU 32A PV Industrial (-40°C to 85°C) Note: All packages are Pb free, fully LHF. Package Type 32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP) PV PV, 32-lead, 7.0mm × 7.0mm body, 0.65mm pitch quad flat no lead package (QFN) 2.2. ATmega32M1 Speed [MHz] Power Supply [V] Ordering Code Package Operational Range 16 2.7 - 5.
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3. Overview The Atmel ATmega16M1/32M1/64M1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16M1/32M1/64M1 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block diagram Figure 3-1. Block diagram.
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programmable Watchdog Timer with Internal Individual Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset.
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Alternate Functions of Port C on page 103 3.2.5. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
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4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
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5. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation.
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6. Data retention Reliability Qualification results show that the projected data retention failure rate is much less than 1ppm over 20 years at 85°C or 100 years at 25°C.
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7. AVR CPU Core 7.1. Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1.
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The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format.
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7.3.1. Status Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. 7.4. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
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Figure 7-3. The X-, Y-, and Z-registers 15 X-register XH 7 0 15 Y-register 7 R26 YH YL 0 7 R28 ZH ZL 0 7 R31 0 0 R29 7 0 0 R27 7 15 Z-register XL 0 0 R30 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). Related Links Instruction Set Summary on page 419 7.5.
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7.5.1. Stack Pointer Register Low and High byte The SPL and SPH register pair represents the 16-bit value, SP.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
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7.5.2. Stack Pointer Register Low and High byte The SPL and SPH register pair represents the 16-bit value, SP.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
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7.5.3. Stack Pointer Register Low and High byte The SPL and SPH register pair represents the 16-bit value, SP.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
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7.7. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. The Figure below shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts: The first type is triggered by an event that sets the Interrupt Flag.
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C Code Example(1) __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 1. Refer to About Code Examples. Related Links Memory Programming on page 375 Boot Loader Support – Read-While-Write Self-Programming on page 356 7.8.1. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum.
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8. AVR Memories 8.1. Overview This section describes the different memory types in the device. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the device features an EEPROM Memory for data storage. All memory spaces are linear and regular. 8.2. In-System Reprogrammable Flash Program Memory The ATmega16M1/32M1/64M1 contains 16/32/64Kbytes On-chip In-System Reprogrammable Flash memory for program storage.
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Figure 8-2. Program Memory Map ATmega32M1 Program Memory 0x0000 Application Flash Section Boot Flash Section 0x3FFF Figure 8-3. Program Memory Map ATmega64M1 Program Memory 0x0000 Application Flash Section Boot Flash Section 0x7FFF Related Links BTLDR - Boot Loader Support – Read-While-Write Self-Programming on page 356 MEMPROG- Memory Programming on page 375 Instruction Execution Timing on page 29 8.3. SRAM Data Memory The following figure shows how the device SRAM Memory is organized.
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The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 2304 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM.
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Figure 8-5. Data Memory Map with 2048 byte internal data SRAM (2048x8) 0x08FF Figure 8-6. Data Memory Map with 4096 byte internal data SRAM (4096x8) 0x10FF 8.3.1. Data Memory Access Times The internal data SRAM access is performed in two clkCPU cycles as described in the following Figure.
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Figure 8-7. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 8.4. Next Instruction EEPROM Data Memory The ATmega16M1/32M1/64M1 contains 512B/1K/2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
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8.4.2. Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
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8.6. Register Description 8.6.1. Accessing 16-bit Registers The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register using a 16-bit bus. For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte is then written into the temporary register.
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8.6.2. EEPROM Address Register Low and High Byte The EEARL and EEARH register pair represents the 16-bit value, EEAR. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used.
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8.6.3. EEPROM Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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8.6.4. EEPROM Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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must be written to '1' before EEPE is written to '1', otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEPE becomes zero. 2. Wait until SPMEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a '1' to the EEMPE bit while writing a zero to EEPE in EECR. 6.
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rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example(1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
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8.6.5. GPIOR2 – General Purpose I/O Register 2 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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8.6.6. GPIOR1 – General Purpose I/O Register 1 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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8.6.7. GPIOR0 – General Purpose I/O Register 0 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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9. System Clock and Clock Options 9.1. Clock Systems and Their Distribution The following figure illustrates the principal clock systems in the device and their distribution. All the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes. The clock systems are described in the following sections. The system clock frequency refers to the frequency generated from the System Clock Prescaler.
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9.1.2. I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but the start condition detection in the USI module is carried out asynchronously when clkI/O is halted, TWI address recognition in all sleep modes.
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Device Clocking Option System clock PLL input CKSEL[3:0] PLL output divided by 4 : PLL/4 16MHz RC osc 0011 Calibrated Internal RC Oscillator RC osc 0010 PLL output divided by 4 : PLL/4 16MHz / PLL driven by external clock Ext clk 0001 External Clock RC osc 000 RC osc Ext clk Note: For all fuses, '1' means unprogrammed while '0' means programmed. The various choices for each clocking option is given in the following sections.
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Figure 9-2. Crystal oscillator connections C2 XTAL2 C1 XTAL1 GND The oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in the table below. Table 9-3. Crystal oscillator operating modes CKSEL3..1 Frequency range [MHz] Recommended range for capacitors C1 and C2 for use with crystals [pF] 100(1) 0.4 - 0.9 - 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 -16.
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CKSEL0 SUT1..0 Start-up time from Additional delay Recommended power-down and from reset (VCC = usage power-save 5.0V) 1 10 16K CK 14CK + 4.1ms Ceramic resonator, fast rising power 1 11 16K CK 14CK + 65ms Ceramic resonator, slowly rising power 1. 2. Note: These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.
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Table 9-6. Start-Up Times for the Internal Calibrated RC Oscillator Clock Selection - SUT Power Conditions Start-Up Time from Power-down and Power-Save Additional Delay from Reset (VCC = 5.0V) SUT[1:0] BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4ms 01 14CK + 65ms 10(1) Slowly rising power 6 CK Reserved 11 Note: 1. The device is shipped with this option selected. Related Links System Clock Prescaler on page 54 Calibration Byte on page 379 OSCCAL on page 56 9.6. PLL 9.6.1.
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CKSEL 3..0 0101 Ext Osc 0001 Ext Clk SUT1..0 Start-up time from power-down and power-save Additional delay from reset (VCC = 5.0V) 00 1K CK 14CK 01 1K CK 14CK + 4ms 10 16K CK 14CK + 4ms 11 16K CK 14CK + 64ms 00 6 CK(1) 14CK 01 6 CK(1) 14CK + 4ms 10 6 CK(1) 14CK + 64ms Reserved Note: This value do not provide a proper restart; do not use PD in this clock scheme. Figure 9-3.
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Table 9-8. External Clock Frequency CKSEL[3:0] Frequency 0000 0 - 16MHz When this clock source is selected, start-up times are determined by the SUT Fuses: Table 9-9. Start-Up Times for the External Clock Selection - SUT SUT[1:0] Start-Up Time from Power-down and Powersave Additional Delay from Reset (VCC = 5.0V) Recommended Usage 00 6 CK 14CK BOD enabled 01 6 CK 14CK + 4.
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interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. 2. Write the Clock Prescaler Change Enable (CLKPCE) bit to '1' and all other bits in CLKPR to zero: CLKPR=0x80.
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9.11.1. Oscillator Calibration Register Name: OSCCAL Offset: 0x66 Reset: Device Specific Calibration Value Property: - Bit Access Reset 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 – CALn: Oscillator Calibration Value [n = 7:0] The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
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9.11.2. PLL Control and Status Register Name: PLLCSR Offset: 0x49 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 Access Reset 2 1 0 PLLF PLLE PLOCK R/W R/W R 0 x 0 Bit 2 – PLLF: PLL Factor The PLLF bit is used to select the division factor of the PLL. Value 1 0 Description If PLLF is set, the PLL output is 64MHz. If PLLF is cleared, the PLL output is 32MHz.
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9.11.3. Clock Prescaler Register Name: CLKPR Offset: 0x61 Reset: Refer to the bit description Property: - Bit Access Reset 3 2 1 0 CLKPCE 7 6 5 4 CLKPS3 CLKPS2 CLKPS1 CLKPS0 R/W R/W R/W R/W R/W 0 x x x x Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
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CLKPS[3:0] Clock Division Factor 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Atmel ATmega16M1/32M1/64M1 [DATASHEET] Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016 59
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10. 10.1. PM - Power Management and Sleep Modes Sleep Modes The following Table shows the different sleep modes and their wake-up sources. Table 10-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Sleep Mode Active Clock Domains clkCPU clkFLASH Idle ADC Noise Reduction Oscillators Wake-up Sources clkIO clkADC clkPLL Main Clock Source Enabled INT3..
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10.3. ADC Noise Reduction Mode When the SM[2:0] bits are written to '001', the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire Serial Interface address watch, Timer/Counter(1), and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run.
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Related Links PSC clock sources on page 197 EXINT - External Interrupts on page 82 10.5. Standby Mode When the SM[2:0] bits are written to '110' and an external clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-Down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. 10.6.
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10.7.4. Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-Out Detection, the Analog Comparator or the Analog-to-Digital Converter. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately.
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10.8.1. Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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10.8.2. Power Reduction Register Name: PRR Offset: 0x64 Reset: 0x00 Property: R/W Bit Access Reset 7 6 5 4 3 2 1 0 PRCAN PRPSC PRTIM1 PRTIM0 PRSPI PRLIN PRADC R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bit 6 – PRCAN: Power Reduction CAN Writing a logic one to this bit reduces the consumption of the CAN by stopping the clock to this module. When waking up the CAN again, the CAN should be re initialized to ensure proper operation.
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11. SCRST - System Control and Reset 11.1. Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.
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Figure 11-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER RSTDISBL Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.3. Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The POR is activated whenever VCC is below the detection level.
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Figure 11-3. MCU Start-up, RESET Extended Externally VCC VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET 11.4. External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
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Figure 11-5. Brown-out Reset During Operation VCC VBOT+ VBOT- RESET t TOUT TIME-OUT INTERNAL RESET 11.6. Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Figure 11-6. Watchdog System Reset During Operation CC CK 11.7. Internal Voltage Reference The device features an internal bandgap reference.
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11.8. Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Watchdog System Reset for details on how to configure the watchdog timer. Features • • • • 11.8.2.
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The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows: 1.
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The following code examples shows how to change the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR ori r16, (1<
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11.9.1. MCU Status Register To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used.
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11.9.2. WDTCSR – Watchdog Timer Control Register Name: WDTCSR Offset: 0x60 Reset: 0x00 Property: Bit Access Reset 7 6 5 4 3 WDIF WDIE WDP[3] WDCE WDE 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 WDP[2:0] Bit 7 – WDIF: Watchdog Interrupt Flag This bit is set when a timeout occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
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Bit 3 – WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe startup after the failure. Bits 2:0 – WDP[2:0]: Watchdog Timer Prescaler 2, 1, and 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.
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12. INT- Interrupts This section describes the specifics of the interrupt handling of the device. For a general explanation of the AVR interrupt handling, refer to the description of Reset and Interrupt Handling. In general: • • Each Interrupt Vector occupies . The Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR. Related Links Reset and Interrupt Handling on page 29 12.1. Interrupt Vectors in ATmega16M1/32M1/64M1 Table 12-1.
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Vector No Program Address Source Interrupts definition 23 0x002C PCINT0 Pin change interrupt request 0 24 0x002E PCINT1 Pin change interrupt request 1 25 0x0030 PCINT2 Pin change interrupt request 2 26 0x0032 PCINT3 Pin change interrupt request 3 27 0x0034 SPI, STC SPI serial transfer complete 28 0x0036 ADC ADC conversion complete 29 0x0038 WDT Watchdog time-out interrupt 30 0x003A EE READY EEPROM ready 31 0x003C SPM READY Store program memory ready Note: 1.
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0x01C jmp TIM1_OVF ; Timer1 Overflow Handler 0x01E jmp TIM0_COMPA ; Timer0 Compare A Handler 0x020 jmp TIM0_COMPB ; Timer0 Compare B Handler 0x022 jmp TIM0_OVF ; Timer0 Overflow Handler 0x024 jmp CAN_INT ; CAN MOB,Burst,General Errors Handler 0x026 jmp CAN_TOVF ; CAN Timer Overflow Handler 0x028 jmp LIN_TC ; LIN Transfer Complete Handler 0x02A jmp LIN_ERR ; LIN Error Handler 0x02C jmp PCINT0 ; Pin Change Int Request 0 Handler 0x02E jmp PCINT1 ; Pin Change Int Request 1 Handler 0x030 jmp PCINT2 ; Pin Change
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... ... ... ; 0xC3C jmp SPM_RDY ; Store Program Memory Ready Handler ; 0xC3E RESET: ldi r16,high(RAMEND); Main program start 0xC3F out SPH,r16 ; Set Stack Pointer to top of RAM 0xC40 ldi r16,low(RAMEND) 0xC41 out SPL,r16 0xC42 sei ; Enable interrupts 0xC43 xxx 12.2. Register Description 12.2.1. Moving Interrupts Between Application and Boot Space The MCU Control Register controls the placement of the Interrupt Vector table.
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12.2.2. MCU Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
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13. External Interrupts 13.1. EXINT - External Interrupts The External Interrupts are triggered by the INT pin or any of the PCINT pins. Observe that, if enabled, the interrupts will trigger even if the INT or PCINT pins are configured as outputs. This feature provides a way of generating a software interrupt. The Pin Change Interrupt Request 3 (PCI3) will trigger if any enabled PCINT[31:24] pin toggles. The Pin Change Interrupt Request 2 (PCI2) will trigger if any enabled PCINT[23:16] pin toggles.
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Figure 13-1. Timing of pin change interrupts 0 PCINT[i] pin D Q pin_lat D Q pin_sync LE PCINT[i] bit (of PCMSKn) clk pcint_sync pcint_in[i] D Q pcint_set/flag D Q D 7 Q PCIFn (interrupt flag) clk clk PCINT[i] pin pin_lat pin_sync pcint_in[i] pcint_syn pcint_set/flag PCIFn 13.2.
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13.2.1. External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control.
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Value 00 01 10 11 Description The low level of INT1 generates an interrupt request. Any logical change on INT1 generates an interrupt request. The falling edge of INT1 generates an interrupt request. The rising edge of INT1 generates an interrupt request. Bits 1:0 – ISC0n: Interrupt Sense Control 0 [n = 1:0] The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.
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13.2.2. External Interrupt Mask Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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13.2.3. External Interrupt Flag Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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13.2.4. Pin Change Interrupt Control Register Name: PCICR Offset: 0x68 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCIE3 PCIE2 PCIE1 PCIE0 R/W R/W R/W R/W 0 0 0 0 Bit 3 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 3 is enabled. Any change on any enabled PCINT[31:24] pin will cause an interrupt.
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13.2.5. Pin Change Interrupt Flag Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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13.2.6. Pin Change Mask Register 3 Name: PCMSK3 Offset: 0x6D Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCINT26 PCINT25 PCINT24 R/W R/W R/W 0 0 0 Bits 0, 1, 2 – PCINT24, PCINT25, PCINT26: Pin Change Enable Mask Each PCINT[26:24]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[26:24] is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin.
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13.2.7. Pin Change Mask Register 2 Name: PCMSK2 Offset: 0x6C Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT16, PCINT17, PCINT18, PCINT19, PCINT20, PCINT21, PCINT22, PCINT23: Pin Change Enable Mask Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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13.2.8. Pin Change Mask Register 1 Name: PCMSK1 Offset: 0x6B Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT8, PCINT9, PCINT10, PCINT11, PCINT12, PCINT13, PCINT14, PCINT15: Pin Change Enable Mask Each PCINT[15:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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13.2.9. Pin Change Mask Register 0 Name: PCMSK0 Offset: 0x6A Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – PCINTn: Pin Change Enable Mask [n = 7:0] Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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14. I/O-Ports 14.1. Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
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14.2. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows the functional description of one I/O-port pin, here generically called Pxn. Figure 14-2.
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14.2.2. Toggling the Pin Writing a '1' to PINxn toggles the value of PORTxn, independent on the value of DDRxn. The SBI instruction can be used to toggle one single bit in a port. 14.2.3. Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
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region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in the following figure.
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i = PINB; ... 14.2.5. Digital Input Enable and Sleep Modes As shown in the figure of General Digital I/O, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins.
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Figure 14-5.
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Table 14-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
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Table 14-3.
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• • enabled as a master, the data direction of this pin is controlled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the – PORTB7 bit. – PCINT7, Pin Change Interrupt 7. ADC7/PSCOUT1B/PCINT6 – Bit 6 – ADC7, Analog to Digital Converter, input channel 7. – PSCOUT1B, Output 1B of PSC. – PCINT6, Pin Change Interrupt 6. ADC6/INT2/ACMPN1/AMP2-/PCINT5 – Bit 5 – – • • • • • ADC6, Analog to Digital Converter, input channel 6. INT2, External Interrupt source 2.
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– – PSCOUT2A, Output 2A of PSC. PCINT0, Pin Change Interrupt 0. The tables below relate the alternate functions of Port B to the overriding signals shown in Figure 14-5. Table 14-4. Overriding Signals for Alternate Functions in PB7...
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Table 14-6.
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– • AMP2+, Analog Differential Amplifier 2 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Amplifier. – PCINT15, Pin Change Interrupt 15. ADC10/ACMP1/PCINT14 – Bit 6 – ADC10, Analog to Digital Converter, input channel 10. – ACMP1, Analog Comparator 1 Positive Input.
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• driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTD0 bit. – PCINT9, Pin Change Interrupt 9. PCINT8/PSCOUT1A/INT3 – Bit 0 – PSCOUT1A, Output 1A of PSC. – INT3, External Interrupt source 3: This pin can serve as an external interrupt source to the MCU. – PCINT8, Pin Change Interrupt 8.
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14.3.3. Alternate Functions of Port D The Port D pins with alternate functions are shown in the table below: Table 14-9.
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• • • • • ACMP0/PCINT23 – Bit 7 – ACMP0, Analog Comparator 0 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. – PCINT23, Pin Change Interrupt 23. ADC3/ACMPN2/INT0/PCINT22 – Bit 6 – ADC3, Analog to Digital Converter, input channel 3. – ACMPN2, Analog Comparator 2 Negative Input.
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• • • is enabled as a master, the data direction of this pin is controlled by DDD3. When the pin is forced to be an input, the pull-up can still be controlled by the – PORTD3 bit. – PCINT19, Pin Change Interrupt 19. PCINT18/PSCIN2/OC1A/MISO_A, Bit 2 – PCSIN2, PSC Digital Input 2. – OC1A, Output Compare Match A output: This pin can serve as an external output for the Timer/Counter1 Output – Compare A. The pin has to be configured as an output (DDD2 set “one”) to serve this function.
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Table 14-11.
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• • PCINT25/XTAL1/OC0B – Bit 1 – XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. – OC0B, Output Compare Match B output: This pin can serve as an external output for the Timer/Counter0 Output – Compare B. The pin has to be configured as an output (DDE1 set “one”) to serve this function. This pin is also the output pin for the PWM mode timer function.
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14.4.1. MCU Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
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14.4.2. Port B Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.3. Port B Data Direction Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.4. Port B Input Pins Address When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.5. Port C Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.6. Port C Data Direction Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.7. Port C Input Pins Address When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.8. Port D Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.9. Port D Data Direction Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.10. Port D Input Pins Address When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.11. Port E Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.12. Port E Data Direction Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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14.4.13. Port E Input Pins Address When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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15. TC0 - 8-bit Timer/Counter0 with PWM Related Links Timer/Counter0 and Timer/Counter1 Prescalers on page 183 15.1. Features • • • • • • • 15.2.
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Figure 15-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic Clock Select clkTn Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn =0 = OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA Fixed TOP Value Waveform Generation = OCnB OCRnB TCCRnA 15.2.1. OCnB (Int.Req.
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15.2.2. MAX The counter reaches its Maximum when it becomes 0xF (decimal , for 8-bit counters) or 0xFF (decimal , for 16-bit counters). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value MAX or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation. Registers The Timer/Counter 0 register (TCNT0) and Output Compare TC0x registers (OCR0x) are 8-bit registers.
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Table 15-2. Signal description (internal signals) Signal Name Description count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero).
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Figure 15-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn[1:0] COMnx[1:0] Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B). The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. When double buffering is enabled, the CPU has access to the OCR0x Buffer Register.
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The setup of the OCx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCx value is to use the Force Output Compare (FOCx) strobe bits in Normal mode. The OCx Registers keep their values even when changing between Waveform Generation modes. Be aware that the TCCRA.COMx[1:0] bits are not double buffered together with the compare value. Changing the TCCRA.COMx[1:0] bits will take effect immediately.
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pin (DDR.OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x register state before the output is enabled. Some TCCR0A.COM0x[1:0] bit settings are reserved for certain modes of operation. The TCCR0A.COM0x[1:0] bits have no effect on the Input Capture unit. Related Links Register Description on page 138 15.6.1.
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OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the counting of external events. The timing diagram for the CTC mode is shown below. The counter value (TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 15-5.
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rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In Fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the Fast PWM mode is shown below. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the singleslope operation.
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have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A=0x00. This feature is similar to the OC0A toggle in CTC mode, except double buffering of the Output Compare unit is enabled in the Fast PWM mode. 15.7.4. Phase Correct PWM Mode The Phase Correct PWM mode (WGM0[2:0]=0x1 or WGM0[2:0]=0x5) provides a high resolution, phase correct PWM waveform generation. The Phase Correct PWM mode is based on dual-slope operation: The counter counts repeatedly from BOTTOM to TOP, and then from TOP to BOTTOM.
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setting) the OC0x Register at the compare match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using Phase Correct PWM can be calculated by: �OCnxPCPWM = �clk_I/O � ⋅ 510 N represents the prescaler factor (1, 8, 64, 256, or 1024).
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Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B). The next figure shows the setting of OCF0B in all modes and OCF0A in all modes (except CTC mode and PWM mode where OCR0A is TOP). Figure 15-10.
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Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B). 15.9.
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15.9.1. TC0 Control Register A When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details. The table below shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode. Table 15-5. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected.
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COM0B1 COM0B0 Description 1 0 Clear OC0B on Compare Match, set OC0B at BOTTOM, (non-inverting mode) 1 1 Set OC0B on Compare Match, clear OC0B at BOTTOM, (inverting mode) Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. Refer to Fast PWM Mode for details. The table below shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode. Table 15-8.
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15.9.2. TC0 Control Register B When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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Table 15-10. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
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15.9.3. TC0 Interrupt Mask Register Name: TIMSK0 Offset: 0x6E Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 OCIEB OCIEA TOIE R/W R/W R/W 0 0 0 Bit 2 – OCIEB: Timer/Counter0, Output Compare B Match Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in TIFR0.
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15.9.4. General Timer/Counter Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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15.9.5. TC0 Counter Value Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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15.9.6. TC0 Output Compare Register A When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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15.9.7. TC0 Output Compare Register B When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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15.9.8. TC0 Interrupt Flag Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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16. TC1 - 16-bit Timer/Counter1 with PWM Related Links Timer/Counter0 and Timer/Counter1 Prescalers on page 183 16.1. Overview The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. A block diagram of the 16-bit Timer/Counter is shown below. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in Register Description.
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16.3. Block Diagram Figure 16-1. 16-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA TCCRnB See the related links for actual pin placement.
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Table 16-1. Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00 for 8-bit counters, or 0x0000 for 16-bit counters). 16.5. MAX The counter reaches its Maximum when it becomes 0xF (decimal , for 8-bit counters) or 0xFF (decimal , for 16-bit counters). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value MAX or the value stored in the OCR1A Register.
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Accessing the low byte triggers the 16-bit read or write operation: When the low byte of a 16-bit register is written by the CPU, the high byte that is currently stored in TEMP and the low byte being written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the TEMP register in the same clock cycle as the low byte is read, and must be read subsequently.
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Assembly Code Example(1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret The assembly code example returns the TCNT1 value in the r17:r16 register pair.
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} /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 16.6.1.
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Table 16-2. Signal description (internal signals) Signal Name Description Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero).
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Figure 16-3. Input Capture Unit Block Diagram for TC1 DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO* Analog Comparator ACIC* TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.) ICPn Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B).
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the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin. The edge detector is also identical.
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bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation, see Modes of Operation. A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Below is a block diagram of the Output Compare unit.
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copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to Accessing 16-bit Registers. 16.10.1. Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (TCCR1C.FOC1x) bit.
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Figure 16-5. Compare Match Output Unit, Schematic COMnx[1] COMnx[0] FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the TCCR1A.COM1x[1:0] bits are set.
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Related Links Timer/Counter Timing Diagrams on page 169 Compare Match Output Unit on page 160 16.12.1. Normal Mode The simplest mode of operation is the Normal mode (TCCR1A.WGM1[3:0]=0x0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX=0xFFFF) and then restarts from BOTTOM=0x0000. In normal operation the Timer/Counter Overflow Flag (TIFR1.
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An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag, depending on the actual CTC mode. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. Note: Changing TOP to a value close to BOTTOM while the counter is running must be done with care, since the CTC mode does not provide double buffering.
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TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT1 slopes mark compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 16-7.
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In Fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Writing the COM1x[1:0] bits to 0x2 will produce an inverted PWM and a non-inverted PWM output can be generated by writing the COM1x[1:0] to 0x3. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x).
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diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT1 slopes mark compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 16-8.
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the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements.
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Figure 16-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx[1:0] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B).
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Note: • The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). • N represents the prescale divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode.
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Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The next figure shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 16-12.
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16.14.1. TC1 Control Register A Name: TCCR1A Offset: 0x80 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 1 0 COM1 COM1 COM1 COM1 3 2 WGM11 WGM10 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 4, 5, 6, 7 – COM1, COM1, COM1, COM1: Compare Output Mode for Channel The COM1A[1:0] and COM1B[1:0] control the Output Compare pins (OC1A and OC1B respectively) behavior.
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COM1A1/ COM1B1 COM1A0/ COM1B0 Description 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM (non-inverting mode) 1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM (inverting mode) Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.
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Mode WGM13 WGM12 WGM11 WGM10 (CTC1)(1) (PWM11)(1) (PWM10)(1) Timer/ Counter TOP Update of TOV1 Flag OCR1x at Set on Mode of Operation 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 5 0 1 0 0 CTC OCR1A Immediate MAX 1 Fast PWM, 8bit 0x00FF BOTTOM TOP 6 0 1 1 0 Fast PWM, 9bit 0x01FF BOTTOM TOP 7 0 1 1 1 Fast PWM, 10bit 0x03FF BOTTOM TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and
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16.14.2. TC1 Control Register B Name: TCCR1B Offset: 0x81 Reset: 0x00 Property: - Bit Access 7 6 4 3 2 1 0 ICNC1 ICES1 WGM13 WGM12 CS12 CS11 CS10 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Reset 5 Bit 7 – ICNC1: Input Capture Noise Canceler Writing this bit to '1' activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered.
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CS12 CS11 CS10 Description 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge.
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16.14.3. TC1 Control Register C Name: TCCR1C Offset: 0x82 Reset: 0x00 Property: - Bit Access Reset 7 6 FOC1A FOC1B R/W R/W 0 0 5 4 3 2 1 0 Bit 7 – FOC1A: Force Output Compare for Channel A Bit 6 – FOC1B: Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
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16.14.4. TC1 Counter Value Low and High byte The TCNT1L and TCNT1H register pair represents the 16-bit value, TCNT1.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
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16.14.5. Input Capture Register 1 Low and High byte The ICR1L and ICR1H register pair represents the 16-bit value, ICR1.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
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16.14.6. Output Compare Register 1 A Low and High byte The OCR1AL and OCR1AH register pair represents the 16-bit value, OCR1A.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
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16.14.7. Output Compare Register 1 B Low and High byte The OCR1BL and OCR1BH register pair represents the 16-bit value, OCR1B.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
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16.14.8. Timer/Counter 1 Interrupt Mask Register Name: TIMSK1 Offset: 0x6F Reset: 0x00 Property: - Bit Access Reset 7 6 2 1 0 ICIE 5 4 3 OCIEB OCIEA TOIE R/W R/W R/W R/W 0 0 0 0 Bit 5 – ICIE: Input Capture Interrupt Enable When this bit is written to '1', and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector is executed when the ICF Flag, located in TIFR1, is set.
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16.14.9. TC1 Interrupt Flag Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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17. Timer/Counter 0, 1 Prescalers The 8-bit Timer/Counter0 (TC0) , 16-bit Timer/Counters 1 (TC1) share the same prescaler module, but the Timer/Counters can have different prescaler settings. The following description applies to: TC0 , TC1 . Related Links 8-bit Timer/Counter0 with PWM on page 126 16-bit Timer/Counter1 with PWM on page 150 17.1. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0]=0x1).
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The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling.
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17.4.1. General Timer/Counter Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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18. PSC – power stage controller 18.1. Features • • • • • • • • 18.2.
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PSC description Figure 18-1. Power Stage Controller block diagram. PSC Counter CLKIO Prescaler CLKPLL POCR_RB = module 0 POCR0SB DATABUS 18.4.
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As can be seen from the block diagram, the PSC is composed of three modules. Each of the three PSC modules can be seen as two symmetrical entities. One entity named part A which generates the output PSCOUTnA and the second one named part B which generates the PSCOUTnB output. Each module has its own PSC Input circuitry which manages the corresponding input. 18.5. Functional description 18.5.1. Generating control waveforms In general, the drive of a 3-phase motor requires generating six PWM signals.
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Figure 18-3. Cycle presentation in Centered mode. One P S C cycle P S C counte r va lue UPDATE The figures above graphically illustrate the values held in the PSC counter. Centered mode is like One Ramp mode which counts down and then up. Notice that the update of the waveform generator registers is done regardless of ramp mode at the end of the PSC cycle. 18.5.3.
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Figure 18-4. PSCOUTnA & PSCOUTnB basic waveforms in One Ramp mode. P OCRnRB P OCRnS B P OCRnRA P S C counte r P OCRnS A 0 On-time A On-time B P S COUTnA P S COUTnB De a d-time B De a d-time A P S C cycle On-Time A = (POCRnRAH/L - POCRnSAH/L) × 1/Fclkpsc On-Time B = (POCRnRBH/L - POCRnSBH/L) × 1/Fclkpsc Dead-Time A = (POCRnSAH/L + 1) × 1/Fclkpsc Dead-Time B = (POCRnSBH/L - POCRnRAH/L) × 1/Fclkpsc Note: Minimal value for Dead-time A = 1/Fclkpsc.
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Figure 18-6. PSCOUTnA & PSCOUTnB basic waveforms in Center Aligned mode. P OCRnRB P S C counte r P OCRnS B P OCRnS A 0 On-time 0 On-time 1 On-time 1 P S COUTnA P S COUTnB De a d-time De a d-time P S C cycle On-Time 0 = 2 × POCRnSAH/L × 1/Fclkpsc On-Time 1 = 2 × (POCRnRBH/L - POCRnSBH/L + 1) × 1/Fclkpsc Dead-Time = (POCRnSBH/L - POCRnSAH/L) × 1/Fclkpsc PSC Cycle = 2 × (POCRnRBH/L + 1) × 1/Fclkpsc Note: Minimal value for PSC Cycle = 2 × 1/Fclkpsc.
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18.6. Update of values To avoid asynchronous and incoherent values in a cycle, if an update of one of several values is necessary, all values are updated at the same time at the end of the cycle by the PSC. The new set of values is calculated by software and the update is initiated by software. Figure 18-8. Update at the end of complete PSC cycle.
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18.8. Signal description Figure 18-9. PSC external block view. CLK P LL CLK I/O P OCRRB[11:0] P OCR0S B[11:0] P OCR0RA[11:0] P OCR0S A[11:0] P OCR1S B[11:0] P OCR1RA[11:0] P OCR1S A[11:0] P OCR2S B[11:0] P OCR2RA[11:0] P OCR2S A[11:0] 12 P S COUT0A 12 P S COUT0B 12 P S COUT1A P S COUT1B 12 P S COUT2A 12 P S COUT2B 12 AC2O 12 AC1O 12 AC0O 12 P S CIN2 12 P S CIN1 P S CIN0 IRQ P S C 18.8.1. P S CAS Y Input Description Table 18-1.
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Name Description Type width AC1O Analog Comparator 1 Output Signal AC2O Analog Comparator 2 Output Signal Name Description Type width PSCIN0 Input 0 used for fault function Signal PSCIN1 Input 1 used for fault function Signal PSCIN2 Input 2 used for fault function Signal Name Description Type width PSCOUT0A PSC Module 0 Output A Signal PSCOUT0B PSC Module 0 Output B Signal PSCOUT1A PSC Module 1 Output A Signal PSCOUT1B PSC Module 1 Output B Signal PSCOUT2A PSC Module 2 O
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Figure 18-10. PSC input module. PAOCnA (PAOCnB) 0 P S CINn Ana log Compa ra tor n output 0 Digita l filte r 1 1 CLK P S C P IS ELnA (P IS ELnB) P ELEVnA / P CAEnA (P ELEVnB) (P CAEnB) P RFMnA3:0 (P RFMnB3:0) P FLTEnA (P FLTEnB) 2 4 Input proce s s ing (re trigge ring ...) CLK P S C MP S C core (counte r, wave form ge ne ra tor, ...) Control of the s ix outputs P S COUTnA P S COUTnB CLK P S C 18.9.1.
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18.9.1.2. Signal polarity One can select the active edge (edge modes) or the active level (level modes). See PELEVnx bit description in Section "PMICn – PSC Module n Input Control Register", page 144. If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low.
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PSCn input acts indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 18.11. PSC Input Mode 11xb: Halt PSC and wait for software action Figure 18-14. PSC behavior versus PSCn Input A in fault mode 11xb DT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 P S COUTnA P S COUTnB P S Cn input S oftwa re a ction (1) Note: Software action is the setting of the PRUNn bit in PCTLn register. Used in fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on OnTime1/Dead-Time1.
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Figure 18-15. Clock selection. CLK 1 P LL CK CK/4 CK/32 CK/256 01 10 11 P CLKS EL CK 0 I/O 00 CLK P RES CALER P P REn1/0 CLK P S Cn PCLKSELn bit in PSC Control Register (PCTL) is used to select the clock source. PPREn1/0 bits in PSC Control Register (PCTL) are used to select the divide factor of the clock. Table 18-6. Output clock versus selection and prescaler.
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Vector no. Program address Source Interrupt definition 6 0x0005 PSC_End PSC end of Cycle - - - - - - - - 18.16.
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18.16.1. PSC Output Configuration Name: POC Offset: 0xB6 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 POEN2B POEN2A POEN1B POEN1A POEN0B POEN0A 0 0 0 0 0 0 Access Reset Bit 5 – POEN2B: PSC Output 2B Enable Value 0 1 Description I/O pin affected to PSCOUT2B acts as a standard port. I/O pin affected to PSCOUT2B is connected to the PSC module 2 waveform generator B output and is set and clear according to the PSC operation.
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Value 0 1 Description I/O pin affected to PSCOUT0A acts as a standard port. I/O pin affected to PSCOUT0A is connected to the PSC module 0 waveform generator A output and is set and clear according to the PSC operation.
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18.16.2. PSC Synchro Configuration Name: PSYNC Offset: 0xB4 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 PSYNC2[1:0] 2 1 PSYNC1[1:0] 0 PSYNC0[1:0] Access Reset 0 0 0 0 0 0 Bits 0:1, 2:3, 4:5 – PSYNCn: Synchronization Out for ADC Selection Select the polarity and signal source for generating a signal which will be sent from module n to the ADC for synchronization.
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18.16.3. PSC Output Compare SA Register Note: n = 0 to 2 according to module number. The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the PSC counter value. A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the associated pin. The Output Compare Registers are 16-bit and 12-bit in size.
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18.16.4. PSC Output Compare RA Register Note: n = 0 to 2 according to module number. The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the PSC counter value. A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the associated pin. The Output Compare Registers are 16-bit and 12-bit in size.
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18.16.5. PSC Output Compare SB Register Note: n = 0 to 2 according to module number. The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the PSC counter value. A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the associated pin. The Output Compare Registers are 16-bit and 12-bit in size.
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18.16.6. PSC Output Compare RB Register The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the PSC counter value. A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the associated pin. The Output Compare Registers are 16-bit and 12-bit in size.
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18.16.7. PSC Configuration Register Name: PCNF Offset: 0xB5 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 PULOCK PMODE POPB POPA 0 0 0 0 1 0 Access Reset Bit 5 – PULOCK: PSC Update Lock When this bit is set, the Output Compare Registers POCRnRA, POCRnSA, POCRnSB, POCR_RB and the PSC Output Configuration Registers POC can be written without disturbing the PSC cycles. The update of the PSC internal registers will be done if the PULOCK bit is released to zero.
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18.16.8. PSC Control Register Name: PCTL Offset: 0xB7 Reset: 0x0 Property: R/W Bit 7 6 PPRE[1:0] 1 0 PCLKSEL 5 4 3 2 PCCYC PRUN 0 0 0 Access Reset 0 0 Bits 7:6 – PPRE[1:0]: PSC Prescaler Select These two bits select the PSC input clock division factor. All generated waveforms will be modified by this factor.
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18.16.9. PSC Module n Input Control Register The Input Control Registers are used to configure the two PSC’s Retrigger/Fault block A & B. The two blocks are identical, so they are configured on the same way. Name: PMICn Offset: 0xB8 + n*0x01 [n=0..2] Reset: 0x0 Property: R/W Bit 7 6 5 4 3 POVENm PISELm PELEVm PFLTEm PAOCm 0 0 0 0 0 2 1 0 PRFMm[2:0] Access Reset 0 0 0 Bit 7 – POVENm: PSC Module n Overlap Enable Set this bit to deactivate the Overlap Protection. .
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18.16.10. PSC Interrupt Mask Register Name: PIM Offset: 0xBB Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 PEVE2 PEVE1 PEVE PEOPE 0 0 0 0 Access Reset Bit 3 – PEVE2: PSC External Event 2 Interrupt Enable When this bit is set, an external event which can generates a fault on module 2 generates also an interrupt. Bit 2 – PEVE1: PSC External Event 1 Interrupt Enable When this bit is set, an external event which can generates a fault on module 1 generates also an interrupt.
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18.16.11. PSC Interrupt Flag Register Name: PIFR Offset: 0xBC Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 PEV2 PEV1 PEV PEOP 0 0 0 0 Access Reset Bit 3 – PEV2: PSC External Event 2 Interrupt This bit is set by hardware when an external event which can generates a fault on module 2 occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVE2 bit = 0).
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19. SPI – Serial Peripheral Interface 19.1. Features • • • • • • • • 19.2. Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral units, or between several AVR devices.
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Figure 19-1. SPI Block Diagram SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128 Note: Refer to the pin-out description and the IO Port description for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in the figure below. The system consists of two shift registers, and a Master Clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.
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data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 19-2. SPI Master-slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed.
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SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete in r16, SPSR sbrs r16, SPIF rjmp Wait_Transmit ret C Code Example void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<
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PM - Power Management and Sleep Modes on page 60 I/O-Ports on page 94 19.3. SS Pin Functionality 19.3.1. Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. The SPI logic will be reset once the SS pin is driven high.
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The SPI data transfer formats are shown in the following figure. Figure 19-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 1 Bit 6 Bit 2 Bit 5 LSB MSB Figure 19-4.
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19.5.1. MCU Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
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19.5.2. SPI Control Register 0 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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Table 19-4. CPHA0 Functionality CPHA0 Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample Bits 1:0 – SPR0n: SPI0 Clock Rate Select n [n = 1:0] These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the table below. Table 19-5.
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19.5.3. SPI Status Register 0 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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19.5.4. SPI Data Register 0 When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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20. CAN – Controller Area Network 20.1. Features • • • • • • 20.2. Full CAN controller Fully compliant with CAN standard rev 2.0 A and rev 2.0 B Six MOb (Message Object) with their own: – 11 bits of Identifier Tag (rev 2.0 A), 29 bits of Identifier Tag (rev 2.0 B) – 11 bits of Identifier Mask (rev 2.0 A), 29 bits of Identifier Mask (rev 2.
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corresponding binary values and cannot be changed dynamically. The identifier with the lowest binary number has the highest priority. Bus access conflicts are resolved by bit-wise arbitration on the identifiers involved by each node observing the bus level bit for bit. This happens in accordance with the “wired and” mechanism, by which the dominant state overwrites the recessive state. The competition for bus allocation is lost by all nodes with recessive transmission and dominant observation.
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20.3.2.2. CAN extended frame Figure 20-2. CAN extended frames Data frame Bus Idle SOF 11-bit base identifier IDT28..18 SRR IDE 18-bit identifier extension ID17..0 RTR r1 Arbitration Field Interframe Space r0 4-bit DLC DLC4..0 15-bit CRC 0 - 8 bytes Control Field Data Field CRC Field CRC ACK del. ACK del. ACK Field 7 bits End of Frame Intermission Bus Idle 3 bits (Indefinite) Interframe Space Remote frame Bus Idle SOF 11-bit base identifier IDT28..
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Figure 20-3. CAN bit construction CAN frame (producer) Transmission point (producer) Nominal CAN Bit Time Time quantum (producer) Segments (producer) PROP_SEG SYNC_SEG PHASE_SEG_1 PHASE_SEG_2 propagation delay Segments (consumer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 20.3.3.2. Synchronization segment The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, the current bit level is output.
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20.3.3.9. Bit shortening If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in order to adjust the sample point for bit N+1 and the end of the bit time. 20.3.3.10. Synchronization jump width The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resynchronization Jump Width. This segment may not be longer than Phase Segment 2. 20.3.3.
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20.3.5. Errors The CAN protocol signals any errors immediately as they occur. Three error detection mechanisms are implemented at the message level and two at the bit level: 20.3.5.1. Error at message level • • • Cyclic Redundancy Check (CRC) The CRC safeguards the information in the frame by adding redundant check bits at the transmission end. At the receiver these bits are re-computed and tested against the received bits. If they do not agree there has been a CRC error.
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Figure 20-5. CAN controller structure Buffer MOb i MOb i Size = 120 Bytes Low priority Control Status IDtag+IDmask Time stamp MOb scanning Control Status IDtag+IDmask Time stamp Buffer MOb2 Gen. control Gen.
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• Listening mode This mode is transparent for the CAN channel: • • • • enables a hardware loop back, internal TxCAN on internal RxCAN provides a recessive level on TXCAN output pin does not disable RXCAN input pin freezes TEC and REC error counters Figure 20-6. Listening mode. internal TxCAN PD5 TXCAN PD6 RXCAN LISTEN 20.5.2. internal 1 RxCAN 0 Bit timing FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum.
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Figure 20-8. General Structure of a bit period 1 /CLK IO CLK IO Tscl (TQ) Bit rate prescaler F CAN One nominal bit Data Tsyns(5) Notes: 1. 2. 3. 4. 5. Phase error < 0 Phase error > 0 Phase error > 0 Phase error < 0 Synchronization segment: SYNS Tsyns = 1 x Tscl (fixed) Tprs Tphs1 (1) or Tphs1+Tsjw (3) Tphs2 (2) or Tphs2+Tsjw (4) Tbit Sample point 20.5.3. Transmission point Baud rate With no baud rate prescaler (BRP[5..0]=0) the sampling point comes one time quantum too early.
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Figure 20-9. Overload frame. Instructions Resetting OVRQ bit Setting OVRQ bit OVRQ bit OVFG bit RXCDAN Ident "A" Cmd Message Data "A" CRC A Interframe TXCDAN 20.6. Overload Frame Ident "B" Overload Frame Message objects The MOb is a CAN frame descriptor. It contains all information to handle a CAN frame. This means that a MOb has been outlined to allow to describe a CAN message like an object.
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20.6.2.2. Tx data and remote frame 1. Several fields must be initialized before sending: – Identifier tag (IDT) – Identifier extension (IDE) – Remote transmission request (RTRTAG) – Data length code (DLC) – Reserved bit(s) tag (RBnTAG) – Data bytes of message (MSG) 2. 3. The MOb is ready to send a data or a remote frame when the MOb configuration is set (CONMOB). Then, the CAN channel scans all the MObs in Tx configuration, finds the MOb having the highest priority and tries to send it.
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20.6.2.5. Frame buffer receive mode This mode is useful to receive multi frames. The priority between MObs offers a management for these incoming frames. One set MObs (including non-consecutive MObs) is created when the MObs are set in this mode. Due to the mode setting, only one set is possible. A frame buffer completed flag (or interrupt) BXOK - will rise only when all the MObs of the set will have received their dedicated CAN frame. 1. 2. 3. 4. 5. 6. 7. 20.6.3.
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No filtering: to accept all ID’s from 0x000 up to 0x7FF in part A. • • 20.6.4. ID MSK = 000 0000 0000 b ID TAG = xxx xxxx xxxx b MOb page Every MOb is mapped into a page to save place. The page number is the MOb number. This page number is set in CANPAGE register. The other numbers are reserved for factory tests. CANHPMOB register gives the MOb having the highest priority in CANSIT registers. It is formatted to provide a direct entry for CANPAGE register.
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20.7.2. 16-bit timer This timer starts counting from 0x0000 when the CAN controller is enabled (ENFG bit). When the timer rolls over from 0xFFFF to 0x0000, an interrupt is generated (OVRTIM). 20.7.3. Time triggering Two synchronization modes are implemented for TTC (TTC bit): • • synchronization on Start of Frame (SYNCTTC=0) synchronization on End of Frame (SYNCTTC=1) In TTC mode, a frame is sent once, even if an error occurs. 20.7.4.
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20.8.2. Error types • • • • • BERR: Bit error. The bit value which is monitored is different from the bit value sent Note: Exceptions: - Recessive bit sent monitored as dominant bit during the arbitration field and the acknowledge slot - Detecting a dominant bit during the sending of an error frame SERR: Stuff error. Detection of more than five consecutive bit with the same polarity CERR: CRC error (Rx only).
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• • • • Interrupt on error (bit error, stuff error, CRC error, form error, acknowledge error) Interrupt on frame buffer full Interrupt on “Bus Off” setting Interrupt on overrun of CAN timer The general interrupt enable is provided by ENIT bit and the specific interrupt enable for CAN timer overrun is provided by ENORVT bit. Figure 20-14. CAN controller interrupt structure CANGIE.4 CANGIE.5 CANGIE.3 ENTX CANSTMOB.6 TXOK[i] CANSTMOB.5 RXOK[i] CANSTMOB.4 BERR[i] CANSTMOB.3 SERR[i] CANSTMOB.
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When a MOb error occurs and is set in its own CANSTMOB register, no general error is set in CANGIT register. 20.10. Examples of CAN baud rate setting The CAN bus requires very accurate timing especially for high baud rates. It is recommended to use only an external crystal for CAN operations. (Refer to “Bit timing” on page 164 and “Baud rate” on page 165 for timing description and page 179 to page 180 for “CAN Bit Timing Registers”). Table 20-2. Examples of CAN baud rate settings for commonly frequencies.
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fCLKIO [MHz] CAN rate [Kbps] Description 6.000 1000 ---notapplicable--67% (1) 0.166666 12 500 250 200 4.000 Sampling point 75% 80% 125 75% 100 75% 1000 500 Segments TQ [s] Tbit [TQ] Registers Tprs [TQ] Tph1 [TQ] Tph2 [TQ] Tsjw [TQ] CANBT1 CANBT2 CANBT3 5 3 3 1 0x00 0x08 0x24 (2) x ---nodata--- 0.333333 12 5 3 3 1 0x02 0x08 0x25 0.500 8 3 2 2 1 0x04 0x04 0x13 0.333333 15 7 4 3 1 0x02 0x0C 0x35 0.500 10 4 3 2 1 0x04 0x06 0x23 0.
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20.11. Register Description Figure 20-15.
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20.11.1. CAN General Control Register Name: CANGCON Offset: 0xD8 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 ABRQ OVRQ TTC SYNTTC LISTEN TEST ENA/STB SWRES 0 0 0 0 0 0 0 0 Access Reset Bit 7 – ABRQ: Abort Request This is not an auto resettable bit. Value 0 1 Description No request Abort request: a reset of CANEN1 and CANEN2 registers is done.
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Value 0 1 Description No test mode Test mode: intend for factory testing and not for customer use Bit 1 – ENA/STB: Enable / Standby Mode Because this bit is a command and is not immediately effective, the ENFG bit in CANGSTA register gives the true state of the chosen mode. Value 0 1 Description Standby mode: The on-going transmission (if exists) is normally terminated and the CAN channel is frozen (the CONMOB bits of every MOb do not change). The transmitter constantly provides a recessive level.
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20.11.2. CAN General Status Register Name: CANGSTA Offset: 0xD9 Reset: 0x0 Property: R Bit 7 4 3 2 1 0 OVRG 6 5 TXBSY RXBSY ENFG BOFF ERRP 0 0 0 0 0 0 Access Reset Bit 6 – OVRG: Overload Frame Flag This flag does not generate an interrupt. Value 0 1 Description No overload frame Overload frame: set by hardware as long as the produced overload frame is sent Bit 4 – TXBSY: Transmitter Busy This flag does not generate an interrupt.
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Value 0 1 Description No error passive mode Error passive mode Atmel ATmega16M1/32M1/64M1 [DATASHEET] Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016 246
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20.11.3. CAN General Interrupt Register Name: CANGIT Offset: 0xDA Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 CANIT BOFFIT OVRTIM BXOK SERG CERG FERG AERG 0 0 0 0 0 0 0 0 Access Reset Bit 7 – CANIT: General Interrupt Flag This is a read only bit. Value 0 1 Description No interrupt CAN interrupt: image of all the CAN controller interrupts except for OVRTIM interrupt.
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Bit 2 – CERG: CRC Error General Writing a logical one resets this interrupt flag. Value 0 1 Description No interrupt CRC error interrupt: the CRC check on destuffed message does not fit with the CRC field Bit 1 – FERG: Form Error General Writing a logical one resets this interrupt flag.
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20.11.4.
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Value 0 1 Description Interrupt disabled General errors interrupt enabled Bit 0 – ENOVRT: Enable CAN Timer Overrun Interrupt Value 0 1 Description Interrupt disabled CAN timer interrupt overrun enabled Atmel ATmega16M1/32M1/64M1 [DATASHEET] Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016 250
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20.11.5. CAN Enable MOb Registers Name: CANEN Offset: 0xDC Reset: 0x0 Property: R Bit 15 14 7 6 13 12 11 10 9 8 Access Reset Bit 5 4 3 2 1 0 ENMOB5 ENMOB4 ENMOB3 ENMOB2 ENMOB1 ENMOB0 0 0 0 0 0 0 Access Reset Bits 0, 1, 2, 3, 4, 5 – ENMOBn: Enable MOb This bit provides the availability of the MOb. It is set to one when the MOb is enabled (that is, CONMOB1:0 of CANCDMOB register). Once TXOK or RXOK is set to one (TXOK for automatic reply), the corresponding ENMOB is reset.
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20.11.6.
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20.11.7.
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20.11.8. CAN Bit Timing Register 1 Name: CANBT1 Offset: 0xE2 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0 0 0 0 0 0 0 Access Reset Bits 1, 2, 3, 4, 5, 6 – BRPn: Baud Rate Prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing.
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20.11.9. CAN Bit Timing Register 2 Name: CANBT2 Offset: 0xE3 Reset: 0x0 Property: R/W Bit 7 6 5 3 2 1 SJW1 SJW0 4 PRS2 PRS1 PRS0 0 0 0 0 0 0 Access Reset Bits 5, 6 – SJWn: Re-Synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum number of clock cycles.
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20.11.10. CAN Bit Timing Register 3 Name: CANBT3 Offset: 0xE4 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP 0 0 0 0 0 0 0 Access Reset Bits 4, 5, 6 – PHS2n: Phase Segment 2 This phase is used to compensate for phase edge errors. This segment may be shortened by the resynchronization jump width. PHS2[2:0] shall be ≥1 and ≤PHS1[2..
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20.11.11. CAN Timer Control Register Name: CANTCON Offset: 0xE5 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 TPRSC7 TPRSC6 TPRSC5 TPRSC4 TPRSC3 TPRSC2 TPRSC1 TPRSC0 0 0 0 0 0 0 0 0 Access Reset Bits 0, 1, 2, 3, 4, 5, 6, 7 – TPRSCn: CAN Timer Prescaler Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer if the CAN controller is enabled.
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20.11.12. CAN Timer Registers Name: CANTIM Offset: 0xE6 Reset: 0x0 Property: R Bit 15 14 13 12 11 10 9 8 CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8 0 0 0 0 0 0 0 0 Access Reset Bit 7 6 5 4 3 2 1 0 CANTIM7 CANTIM6 CANTIM5 CANTIM4 CANTIM3 CANTIM2 CANTIM1 CANTIM0 0 0 0 0 0 0 0 0 Access Reset Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – CANTIMn: CAN Timer Count CAN timer counter range 0 to 65,535.
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20.11.13. CAN Timer Registers Name: CANTTC Offset: 0xE8 Reset: 0x0 Property: R Bit 15 14 13 12 11 10 9 8 TIMTTC15 TIMTTC14 TIMTTC13 TIMTTC12 TIMTTC11 TIMTTC10 TIMTTC9 TIMTTC8 0 0 0 0 0 0 0 0 Access Reset Bit 7 6 5 4 3 2 1 0 TIMTTC7 TIMTTC6 TIMTTC5 TIMTTC4 TIMTTC3 TIMTTC2 TIMTTC1 TIMTTC0 0 0 0 0 0 0 0 0 Access Reset Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – TIMTTCn: TTC Timer Count CAN TTC timer counter range 0 to 65,535.
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20.11.14. CAN Transmit Error Counter Register Name: CANTEC Offset: 0xEA Reset: 0x0 Property: R Bit 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 0 0 0 0 0 0 0 0 Access Reset Bits 0, 1, 2, 3, 4, 5, 6, 7 – TECn: Transmit Error Count CAN transmit error counter range 0 to 255.
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20.11.15. CAN Receive Error Counter Register Name: CANREC Offset: 0xEB Reset: 0x0 Property: R Bit 7 6 5 4 3 2 1 0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0 0 0 0 0 0 0 0 Access Reset Bits 0, 1, 2, 3, 4, 5, 6, 7 – RECn: Receive Error Count CAN receive error counter range 0 to 255.
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20.11.16. CAN Highest Priority MOb Register Name: CANHPMOB Offset: 0xEC Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 HPMOB3 HPMOB2 HPMOB1 HPMOB0 CGP3 CGP2 CGP1 CGP0 0 0 0 0 0 0 0 0 Access Reset Bits 4, 5, 6, 7 – HPMOBn: Highest Priority MOb Number MOb having the highest priority in CANSIT registers. If CANSIT = 0 (no MOb), the return value is 0xF.
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20.11.17. CAN Page MOb Register Name: CANPAGE Offset: 0xED Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 MOBNB3 MOBNB2 MOBNB1 MOBNB0 AINC INDX2 INDX1 INDX0 0 0 0 0 0 0 0 0 Access Reset Bits 4, 5, 6, 7 – MOBNBn: MOb Number Selection of the MOb number, the available numbers are from 0 to 5.
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20.11.18. CAN MOb Status Register Name: CANSTMOB Offset: 0xEE Reset: Property: R/W Bit 7 6 5 4 3 2 1 0 DLCW TXOK RXOK BERR SERR CERR FERR AERR Access Reset Bit 7 – DLCW: Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of the CANCDMOB register is updated by the received DLC. Bit 6 – TXOK: Transmit OK This flag can generate an interrupt.
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Bit 1 – FERR: Form Error This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The form error results from one or more violations of the fixed form in the following bit fields: • • • CRC delimiter Acknowledgment delimiter EOF Bit 0 – AERR: Acknowledgment Error This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register.
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20.11.19. CAN MOb Control and DLC Register Name: CANCDMOB Offset: 0xEF Reset: Property: R/W Bit 7 6 5 4 3 2 1 0 CONMOB1 CONMOB0 RPLV IDE DLC3 DLC2 DLC1 DLC0 Access Reset Bits 6, 7 – CONMOBn: Configuration of Message Object These bits set the communication to be performed (no initial value after RESET). These bits are not cleared once the communication is performed. The user must re-write the configuration to enable a new communication.
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20.11.20. CAN Identifier Tag Registers V2.0 part A Name: CANIDT Offset: 0xF0 Reset: Property: R/W Bit 31 30 29 28 27 26 25 24 IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 IDT4 IDT3 23 22 21 20 19 18 17 16 IDT2 IDT1 IDT0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit RTRTAG 0 RB0TAG Access Reset Bits 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – IDTn: Identifier Tag Identifier field of the remote or data frame to send.
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20.11.21. CAN Identifier Tag Registers V2.
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20.11.22. CAN Identifier Mask Registers V2.
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20.11.23. CAN Identifier Mask Registers V2.
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20.11.24. CAN Time Stamp Registers Name: CANSTM Offset: 0xF8 Reset: Property: R Bit 15 14 13 12 11 10 9 8 TIMSTM15 TIMSTM14 TIMSTM13 TIMSTM12 TIMSTM11 TIMSTM10 TIMSTM9 TIMSTM8 Access Reset Bit 7 6 5 4 3 2 1 0 TIMSTM7 TIMSTM6 TIMSTM5 TIMSTM4 TIMSTM3 TIMSTM2 TIMSTM1 TIMSTM0 Access Reset Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – TIMSTMn: Time Stamp Count CAN time stamp counter range 0 to 65,535.
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20.11.25. CAN Data Message Register Name: CANMSG Offset: 0xFA Reset: Property: R Bit 7 6 5 4 3 2 1 0 MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0 Access Reset Bits 0, 1, 2, 3, 4, 5, 6, 7 – MSGn: Message Data This register contains the CAN data byte pointed at the page MOb register. After writing in the page MOb register, this byte is equal to the specified message location of the predefined identifier + index.
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21. LIN / UART - Local Interconnect Network Controller or UART 21.1. Features 21.1.1. LIN • Hardware implementation of LIN 2.1 (LIN 1.3 Compatibility) • Small, CPU efficient and independent Master/Slave routines based on “LIN Work Flow Concept” of LIN 2.
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21.3. LIN protocol 21.3.1. Master and slave A LIN cluster consists of one master task and several slave tasks. A master node contains the master task as well as a slave task. All other nodes contain a slave task only. Figure 21-1. LIN cluster with one master node and “n” slave nodes. mas te r no de ma s te r ta s k s lave no de 1 s lave no de n s lave ta s k s lave ta s k s lave ta s k LIN bus The master task decides when and which frame shall be transferred on the bus.
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21.3.4. Schedule table The master task (in the master node) transmits frame headers based on a schedule table. The schedule table specifies the identifiers for each header and the interval between the start of a frame and the start of the following frame. The master application may use different schedule tables and select among them. 21.3.5. Compatibility with LIN 1.3 LIN 2.1 is a super-set of LIN 1.3. A LIN 2.1 master node can handle clusters consisting of both LIN 1.3 slaves and/or LIN 2.1 slaves.
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• • • LRXOK: LIN response received LTXOK: LIN response transmitted LERR: LIN Error(s) The wake-up management can be automated using the UART wake-up capability and a node sending a minimum of five low bits (0xF0) for LIN 2.1 and 8 low bits (0x80) for LIN 1.3. Pin change interrupt on LIN wake-up signal can be also used to exit the device of one of its sleep modes. Extended frame identifiers 62 (0x3E) and 63 (0x3F) are reserved to allow the embedding of user-defined message formats and future LIN formats.
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21.4.4. LIN/UART command overview Figure 21-5. LIN/UART command dependencies. Tx response Tx header IDOK TXOK Tx response Rx header or LIN abort RXOK Automatic return Recommended way LIN DISABLE UART Possible way Byte transfer Rx byte Full duplex Tx byte Table 21-1. LIN/UART command list. LENA LCMD[2] LCMD[1] LCMD[0] Command 0 x x x Disable peripheral 1 0 0 0 Rx Header - LIN abort LIN withdrawal 1 Tx header LCMD[2..0]=000 after Tx 0 Rx response LCMD[2..
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21.4.6. LIN commands Clearing the LCMD[2] bit in LINCR register enables LIN commands. As shown in Table 21-1, four functions controlled by the LCMD[1..0] bits of LINCR register are available (see Figure 21-5). 21.4.6.1. Rx header / LIN abort function This function (or state) is mainly the withdrawal mode of the controller. When the controller has to execute a master task, this state is the start point before enabling a Tx Header command.
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In LIN 1.3, the header slot configures the LINDLR register. In LIN 2.1, the user must configure the LINDLR register, either LRXDL[3..0] for Rx Response either LTXDL[3..0] for Tx Response. When the command starts, the controller checks the LIN13 bit of the LINCR register to apply the right rule for computing the checksum. Checksum calculation over the DATA bytes and the PROTECTED IDENTIFIER byte is called enhanced checksum and it is used for communication with LIN 2.1 slaves.
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The intrinsic structure of the Rx service offers a 2-byte buffer. The fist one is used for serial to parallel conversion, the second one receives the result of the conversion. This second buffer byte is reached reading LINDAT register. If the 2-byte buffer is full, a new in-coming character will overwrite the second one already recorded. An OVRERR error in LINERR register will then accompany this character when read. A FERR error in LINERR register will be set in case of framing error. 21.4.7.3.
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The controller checks the LIN13 bit in computing the checksum (enhanced checksum in LIN2.1 / classic checksum in LIN 1.3). See Rx & TX response functions. This bit is irrelevant for UART commands. 21.5.4. Configuration Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the controller in the following configuration: Table 21-3. Configuration table versus mode. Mode LCONF[1..
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21.5.5.1. Busy signal in LIN mode Figure 21-7.
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21.5.6.2. Re-synchronization in LIN mode When waiting for Rx Header, LBT[5..0] = 32 in LINBTR register. The re-synchronization begins when the BREAK is detected. If the BREAK size is not in the range (11 bits min., 28 bits max. — 13 bits nominal), the BREAK is refused. The re-synchronization is done by adjusting LBT[5..0] value to the SYNCH field of the received header (0x55). Then the PROTECTED IDENTIFIER is sampled using the new value of LBT[5..0].
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21.5.7.2. Data length in LIN 1.3 • • LRXDL and LTXDL fields are both hardware updated before setting LIDOK by decoding the data length code contained in the received PROTECTED IDENTIFIER (LRXDL = LTXDL) Via the above mechanism, a length of 0 or >8 is not possible 21.5.7.3. Data length in Rx Response Figure 21-9. LIN2.1 - Rx Response - no error LIDOK LIN bus LRXDL (*) 4 LTXDL (*) ? LRXOK 1st Byte 2 nd Byte 3 rd Byte 4 th Byte DATA-0 DATA-1 DATA-2 DATA-3 CHECKSUM 1 2 3 4 0 LBUSY LCMD2..
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21.5.7.5. Data length after error Figure 21-11. Tx Response - error. LIN bus 1st Byte 2 nd Byte 3 rd Byte DATA-0 DATA-1 DATA-2 LERR ERROR LRXDL 4 LTXDL 4 0 1 2 LBUSY LCMD2..0=000b LCMD=Tx Response Note: Information on response (ex: error on byte) is only available at the end of the serialization/deserialization of the byte. 21.5.7.6. Data length in UART mode • • 21.5.8.
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• • • • • The hardware does not undertake any correction. However, the LIN slave application has to solve this as: – known identifier (parity bits corrupted) – or corrupted identifier to be ignored – or new identifier LSERR = LIN Synchronization ERRor. A LIN synchronization error will be flagged if a slave detects the edges of the SYNCH field outside the given tolerance. LFERR = LIN Framing ERRor. A framing error will be flagged if dominant STOP bit is sampled. Same function in UART mode.
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On the slave node, the BREAK detection is processed with the synchronization setting available when the LIN/UART controller processed the (aborted) response. But the re-synchronization restarts as usual. Due to a possible difference of timing reference between the BREAK field and the rest of the frame, the timeout values can be slightly inaccurate. 21.5.12. Checksum The last field of a frame is the checksum. In LIN 2.
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Table 21-4. Frame status LIDST[2..0] Frame status 0xx b No specific identifier 100 b 60 (0x3C) identifier 101 b 61 (0x3D) identifier 110 b 62 (0x3E) identifier 111 b 63 (0x3F) identifier The LIN protocol says that a message with an identifier from 60 (0x3C) up to 63 (0x3F) uses a classic checksum (sum over the data bytes only).
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5. 6. 7. – Note that LINERR bits are ORed to provide the LERR interrupt flag of LINSIR LINBTR – LBT[5..0] are R/W access only if LDISR is set – If LDISR is reset, LBT[5..0] are unchangeable LINBRRH & LINBRRL – All bits are R/W accessible LINDLR – All bits are R/W accessible 8. LINIDR – LID[5..0] are R/W accessible – LP[1..0] are Read accessible and are always updated on the fly 9. LINSEL – All bits are R/W accessible 10.
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21.6.1. LIN Control Register Name: LINCR Offset: 0xC8 Reset: 0x0 Property: R/W Bit 7 6 LSWRES LIN13 0 0 5 4 LCONF[1:0] 3 2 LENA 1 0 LCMD[2:0] Access Reset 0 0 0 0 0 0 Bit 7 – LSWRES: Software Reset Value 0 1 Description No action Software reset (this bit is self-reset at the end of the reset procedure) Bit 6 – LIN13: LIN 1.3 mode Value 0 1 Description LIN 2.1 (default) LIN 1.
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Value 011 100 11x 1x1 Description LIN Tx Response UART Rx & Tx Byte disable UART Rx Byte enable UART Tx Byte enable Atmel ATmega16M1/32M1/64M1 [DATASHEET] Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016 291
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21.6.2.
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Value 0 1 Description No Tx Tx Response complete Bit 0 – LRXOK: Receive Performed Interrupt This bit generates an interrupt if its respective enable bit - LENRXOK - is set in LINENIR. The user clears this bit by writing 1, in order to reset this interrupt. In UART mode, this bit is also cleared by writing LINDAT.
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21.6.3.
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21.6.4. LIN Error Register Name: LINERR Offset: 0xCB Reset: 0x0 Property: R Bit 7 6 5 4 3 2 1 0 LABORT LTOERR LOVERR LFERR LSERR LPERR LCERR LBERR 0 0 0 0 0 0 0 0 Access Reset Bit 7 – LABORT: Abort Flag This bit is cleared when LERR bit in LINSIR is cleared. Value 0 1 Description No warning LIN abort command occurred Bit 6 – LTOERR: Frame_Time_Out Error Flag This bit is cleared when LERR bit in LINSIR is cleared.
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Value 0 1 Description No error Parity error Bit 1 – LCERR: Checksum Error Flag This bit is cleared when LERR bit in LINSIR is cleared. Value 0 1 Description No error Checksum error Bit 0 – LBERR: Bit Error Flag This bit is cleared when LERR bit in LINSIR is cleared.
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21.6.5. LIN Bit Timing Register Name: LINBTR Offset: 0xCC Reset: 0x20 Property: R/W Bit 7 6 5 4 3 LDISR 2 1 0 0 0 0 LBT[5:0] Access Reset 0 1 0 0 Bit 7 – LDISR: Disable Bit Timing Re synchronization Value 0 1 Description Bit timing re-synchronization enabled (default) Bit timing re-synchronization disabled Bits 5:0 – LBT[5:0]: LIN Bit Timing Gives the number of samples of a bit. Sample-time = (1/fclki/o ) × (LDIV[11..0] + 1). Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max.
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21.6.6. LIN Baud Rate Register Name: LINBRR Offset: 0xCD Reset: 0x0 Property: R/W Bit 15 14 13 12 11 10 9 8 LDIV11 LDIV10 LDIV9 LDIV8 0 0 0 0 Access Reset Bit 7 6 5 4 3 2 1 0 LDIV7 LDIV6 LDIV5 LDIV4 LDIV3 LDIV2 LDIV1 LDIV0 0 0 0 0 0 0 0 0 Access Reset Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – LDIVn: Scaling of clki/o Frequency The LDIV value is used to scale the entering clki/o frequency to achieve appropriate LIN or UART baud rate.
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21.6.7. LIN Data Length Register Name: LINDLR Offset: 0xCF Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 LTXDL0[3:0] 1 0 0 0 LRXDL0[3:0] Access Reset 0 0 0 0 0 0 Bits 4:7, 8:11, 12:15, 16:19 – LTXDLn: LIN Transmit Data Length In LIN mode, this field gives the number of bytes to be transmitted (clamped to 8 Max). In UART mode this field is unused. Bits 0:3, 4:7, 8:11, 12:15 – LRXDLn: LIN Receive Data Length In LIN mode, this field gives the number of bytes to be received (clamped to 8 Max).
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21.6.8. LIN Identifier Register Name: LINIDR Offset: 0xD0 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 LP1 LP0 LDL1 LDL0 LID3 LID2 LID1 LID0 0 0 0 0 0 0 0 0 Access Reset Bits 6, 7 – LPn: Parity In LIN mode: LP0 = LID4 ^ LID2 ^ LID1 ^ LID0 LP1 = ! ( LID1 ^ LID3 ^ LID4 ^ LID5 ) In UART mode this field is unused. Bits 4, 5 – LDLn: LIN 1.3 Data Length or LIN 2.1 Identifier In LIN 1.3 mode as in the table below. In LIN 2.
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21.6.9. LIN Data Buffer Selection Register Name: LINSEL Offset: 0xD1 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 LAINC1 LAINC0 LINDX2 LINDX1 LINDX0 0 0 0 0 0 Access Reset Bits 3, 4 – LAINCn: Auto Increment of Data Buffer Index In LIN mode as in the table below In UART mode this field is unused.
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21.6.10. LIN Data Register Name: LINDAT Offset: 0xD2 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 LDATA7 LDATA6 LDATA5 LDATA4 LDATA3 LDATA2 LDATA1 LDATA0 0 0 0 0 0 0 0 0 Access Reset Bits 0, 1, 2, 3, 4, 5, 6, 7 – LDATAn: LIN Data In / Data out In LIN mode: FIFO data buffer port. In UART mode: data register (no data buffer - no FIFO).
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22. ADC - Analog to Digital Converter 22.1. Features • • • • • • • • • • • • • • • • • 22.2. 10-bit Resolution 0.5 LSB Integral Non-Linearity ±2 LSB Absolute Accuracy 8 - 250μs Conversion Time Up to 120kSPS at Maximum Resolution 11 Multiplexed Single Ended Input Channels Three differential input channels with accurate (5%) programmable gain 5, 10, 20 and 40 Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
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Figure 22-1. Analog to Digital Converter Block Schematic Operation Curre nt S ource IS RCEN AREF / IS RC IS RC AREFEN AVCC Inte rna l 2.
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Power Reduction Register on page 62 22.3. M1_Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register.
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cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. Figure 22-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished.
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The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100kHz. The prescaling is selected by the ADC Prescaler Select bits in the ADC Control and Status Register A (ADCSRA.ADPS). The prescaler starts counting from the moment the ADC is switched on by writing the ADC Enable bit ADCSRA.ADEN to '1'. The prescaler keeps running for as long as ADEN=1, and is continuously reset when ADEN=0.
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Figure 22-5. ADC Timing Diagram, Single Conversion One Conversion 1 Cycle Number 2 3 4 5 6 Next Conversion 7 8 9 11 12 13 14 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample and Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 22-6.
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Table 22-1. ADC Conversion Time Condition Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 3.5 15.5 Auto Triggered conversions 2 16 22.6. Changing Channel or Reference Selection The Analog Channel Selection bits (MUX) and the Reference Selection bits (REFS) bits in the ADC Multiplexer Selection Register (ADMUX.MUX[3:0] and ADMUX.
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• method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. In Free Running mode, because the amplifier clear the ADSC bit at the end of an amplified conversion, it is not possible to use the free running mode, unless ADSC bit is set again by soft at the end of each conversion.
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Note: The ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADCRSA.ADEN before entering such sleep modes to avoid excessive power consumption. 22.7.1. Analog Input Circuitry The analog input circuitry for single ended channels is illustrated below.
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Analog Ground Plane PA3 (ADC3) PA2 (ADC2) PA1 (ADC1) PA0 (ADC0) VCC GND Figure 22-9. ADC Power Connections PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) AREF 10μH PA7 (ADC7) AVCC 100nF GND PC7 22.7.3. Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs.
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Figure 22-10. Offset Error Output Code Ideal ADC Actual ADC Offset Error • VREF Input Voltage Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB. Figure 22-11.
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• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 22-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 • • 22.8. VREF Input Voltage Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
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Figure 22-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF /GAIN 0x3FF 0 VREF /GAIN Diffe re ntia l Input Volta ge (Volts ) 0x200 The table below shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is selected with a gain of GAIN and a reference voltage of VREF. Table 22-2. Correlation between Input Voltage and Output Codes VADCn Read code Corresponding Decimal Value VADCm + VREF/GAIN 0x1FF 511 VADCm + 0.999 VREF/GAIN 0x1FF 511 VADCm + 0.
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Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. 22.9. Temperature Measurement The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended Temperature sensor channel. Selecting the Temperature sensor channel by writing ADMUX.MUX[4:0] to '10000' enables the temperature sensor. The internal 2.56V voltage reference must also be selected for the ADC voltage reference source in the temperature sensor measurement.
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Where: • ADCH and ADCL are the ADC data registers. • TSGAIN is the temperature sensor gain (constant 1, or unsigned fixed point number, 0x80 = decimal 1.0). • TSOFFSET is the temperature sensor offset correction term (2. complement signed byte). 22.10. Amplifier The Atmel ATmega16M1/32M1/64M1 features three differential amplified channels with programmable 5, 10, 20, and 40 gain stage.
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Figure 22-15. Amplifier synchronization timing diagram. With change on analog input signal.
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Figure 22-16. Amplifier synchronization timing diagram. ADSC is set when the amplifier output is changing due to the amplifier clock switch.
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Figure 22-17. Amplifiers block diagram.
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22.11.1. ADC Multiplexer Selection Register Name: ADMUX Offset: 0x7C Reset: 0x00 Property: R/W Bit Access Reset 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:6 – REFSn: ADC Reference Selection Bits These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).
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Bits 4:0 – MUXn: ADC Channel Selection Bits These four bits determine which analog inputs are connected to the ADC input. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete. (ADIF in ADCSRA is set). Table 22-5.
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22.11.2. ADC Control and Status Register A Name: ADCSRA Offset: 0x7A Reset: 0x00 Property: r/w Bit Access Reset 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will take effect at the end of the conversion.
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ADPS[2:0] Division Factor 011 8 100 16 101 32 110 64 111 128 Atmel ATmega16M1/32M1/64M1 [DATASHEET] Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016 324
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22.11.3. ADC Control and Status Register B Name: ADCSRB Offset: 0x7B Reset: 0x00 Property: R/W Bit Access Reset 7 6 5 ADHSM ISRCEN AREFEN 4 3 R/W R/W R/W R/W 0 0 0 0 2 1 0 R/W R/W R/W 0 0 0 ADTS[3:0] Bit 7 – ADHSM: ADC High Speed Mode Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to convert with an ADC clock frequency higher than 200kHz. Bit 6 – ISRCEN: Current Source Enable Set this bit to source a 100μA current to the AREF pin.
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22.11.4. ADC Data Register Low and High Byte (ADLAR=0) The ADCL and ADCH register pair represents the 16-bit value, ADC Data Register. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When an ADC conversion is complete, the result is found in these two registers.
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22.11.5. ADC Data Register Low and High Byte (ADLAR=1) The ADCL and ADCH register pair represents the 16-bit value, ADC Data Register. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When an ADC conversion is complete, the result is found in these two registers.
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22.11.6. Digital Input Disable Register 0 When the respective bits are written to logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7...0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
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22.11.7. Digital Input Disable Register 1 When the respective bits are written to logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to an analog pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
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22.11.8. Amplifier m Control and Status Register Name: AMP0CSR, AMP1CSR, AMP2CSR Offset: 0x75 + n*0x01 [n=0..2] Reset: 0x00 Property: - Bit Access Reset 7 6 AMPmEN AMPmIS 5 4 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 AMP0G[1:0] 3 2 AMPCMPm 1 0 AMPmTS[2:0] Bit 7 – AMPmEN: Amplifier n Enable Set this bit to enable the Amplifier m. Clear this bit to disable the Amplifier m. Clearing this bit while a conversion is running will take effect at the end of the conversion.
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Value 101 110 111 Description PSC Module 0 synchronization signal (PSS0) PSC Module 1 synchronization signal (PSS1) PSC Module 2 synchronization signal (PSS2) Atmel ATmega16M1/32M1/64M1 [DATASHEET] Atmel-8209F-ATmega16M1/32M1/64M1_Datasheet_Complete-10/2016 331
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23. ISRC - Current Source 23.1. Features • • 100μA constant current source ±2% absolute accuracy The Atmel ATmega16M1/32M1/64M1 features a 100μA ±2% current source. After RESET or up on request, the current is flowing through an external resistor. The voltage can be measured on the dedicated pin shared with the ADC. Using aresistor in series with a ≤0.5% tolerance is recommended.
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Digital converter. The resulting voltage defines the physical address that the communication handler will use when the node will participate in LIN communication. In automotive applications, distributed voltages are very disturbed. The internal Current Source solution of ATmega16M1/32M1/64M1 immunizes the address detection against any kind of voltage variations. Table 23-1.
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Note: 5V range: Max. Rload 30KΩ. 3V range: Max. Rload 15KΩ. 23.2.2. Voltage Reference for External Devices An external resistor used in conjunction with the current source can be used as voltage reference for external devices. Using a resistor in series with a lower tolerance than the Current Source accuracy (≤2%) is recommended. The tables above give examples of voltage references using standard values of resistors. 23.2.3.
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23.3.1. ADC Control and Status Register B Name: ADCSRB Offset: 0x7B Reset: 0x00 Property: R/W Bit Access Reset 7 6 5 ADHSM ISRCEN AREFEN 4 3 R/W R/W R/W R/W 0 0 0 0 2 1 0 R/W R/W R/W 0 0 0 ADTS[3:0] Bit 7 – ADHSM: ADC High Speed Mode Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to convert with an ADC clock frequency higher than 200kHz. Bit 6 – ISRCEN: Current Source Enable Set this bit to source a 100μA current to the AREF pin.
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24. 24.1. AC – analog comparator Features • Four analog comparators • High speed clocked comparators • ±30mV hysteresis • Four reference levels • Generating configurable interrupts 24.2. Overview The Atmel ATmega16M1/32M1/64M1 features four fast analog comparators. The Analog Comparator compares the input values on the positive pin ACMPx and negative pin ACMPM or ACMPMx.
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Figure 24-1.
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24.3. Use of ADC amplifiers Thanks to AMPCMP0 configuration bit, Comparator 0 positive input can be connected to Amplifier O output. In that case, the clock of Comparator 0 is adapted to the Amplifier 0 clock. Thanks to AMPCMP1 configuration bit, Comparator 1 positive input can be connected to Amplifier 1 output. In that case, the clock of Comparator 1 is adapted to the Amplifier 1 clock. Thanks to AMPCMP2 configuration bit, Comparator 2 positive input can be connected to Amplifier 2 output.
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24.4.1. Analog Comparator 0 Control Register Name: AC0CON Offset: 0x94 Reset: 0x0 Property: R/W Bit 7 6 AC0EN AC0IE 0 0 5 4 AC0IS[1:0] 3 2 ACCKSEL 1 0 AC0M[2:0] Access Reset 0 0 0 0 0 0 Bit 7 – AC0EN: Analog Comparator 0 Enable Bit Value 1 0 Description Enable the Analog Comparator 0. Disable the Analog Comparator 0. Bit 6 – AC0IE: Analog Comparator 0 Interrupt Enable bit Value 1 0 Description Enable the Analog Comparator 0 interrupt. Disable the Analog Comparator 0 interrupt.
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24.4.2. Analog Comparator 1 Control Register Name: AC1CON Offset: 0x95 Reset: 0x0 Property: R/W Bit 7 6 AC1EN AC1IE 0 0 5 4 AC1IS[1:0] 3 2 AC1ICE 1 0 AC1M[2:0] Access Reset 0 0 0 0 0 0 Bit 7 – AC1EN: Analog Comparator 1 Enable Bit Value 1 0 Description Enable the Analog Comparator 1. Disable the Analog Comparator 1. Bit 6 – AC1IE: Analog Comparator 1 Interrupt Enable bit Value 1 0 Description Enable the Analog Comparator 1 interrupt. Disable the Analog Comparator 1 interrupt.
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Value 010 011 100 101 110 111 Description “VREF”/2.13 “VREF”/1.60 Bandgap (1.
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24.4.3. Analog Comparator 2 Control Register Name: AC2CON Offset: 0x96 Reset: 0x0 Property: R/W Bit 7 6 AC2EN AC1IE 0 0 5 4 3 2 AC2IS[1:0] 1 0 AC2M[2:0] Access Reset 0 0 0 0 0 Bit 7 – AC2EN: Analog Comparator 2 Enable Bit Value 1 0 Description Enable the Analog Comparator 2. Disable the Analog Comparator 2. Bit 6 – AC1IE: Analog Comparator 2 Interrupt Enable bit Value 1 0 Description Enable the Analog Comparator 2 interrupt. Disable the Analog Comparator 2 interrupt.
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24.4.4. Analog Comparator 3 Control Register Name: AC3CON Offset: 0x97 Reset: 0x0 Property: R/W Bit 7 6 AC3EN AC3IE 0 0 5 4 3 2 AC3IS[1:0] 1 0 AC3M[2:0] Access Reset 0 0 0 0 0 Bit 7 – AC3EN: Analog Comparator 3 Enable Bit Value 1 0 Description Enable the Analog Comparator 3. Disable the Analog Comparator 3. Bit 6 – AC3IE: Analog Comparator 3 Interrupt Enable bit Value 1 0 Description Enable the Analog Comparator 3 interrupt. Disable the Analog Comparator 3 interrupt.
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24.4.5. Analog Comparator Status Register Name: ACSR Offset: 0x50 Reset: 0x0 Property: R/W Bit 7 6 5 4 3 2 1 0 AC3IF AC2IF AC1IF AC0IF AC3O AC2O AC1O AC0O 0 0 0 0 0 0 0 0 Access Reset Bit 7 – AC3IF: Analog Comparator 3 Interrupt Flag Bit This bit is set by hardware when Comparator 3 output event triggers off the interrupt mode defined by AC3IS1 and AC3IS0 bits in AC3CON register.
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Value 1 0 Description The output of the comparator is high. The output comparator is low. Bit 1 – AC1O: AC1O bit is directly the output of the Analog Comparator 1. Value 1 0 Description The output of the comparator is high. The output comparator is low. Bit 0 – AC0O: AC0O bit is directly the output of the Analog Comparator 0. Value 1 0 Description The output of the comparator is high. The output comparator is low.
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24.4.6. Digital Input Disable Register 0 Name: DIDR0 Offset: 0x7E Reset: 0x0 Property: R/W Bit 7 6 5 3 2 ACMPN1D ACMPN0D 4 ACMPN2D ACMP2D 1 ACMPN3D 0 0 0 0 0 0 Access Reset Bit 6 – ACMPN1D: ACMPN1 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding analog pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
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24.4.7. Digital Input Disable Register 1 Name: DIDR1 Offset: 0x7F Reset: 0x0 Property: R/W Bit 7 6 2 1 0 ACMP0D 5 4 3 ACMP1PD ACMP3PD ACMPN3D 0 0 0 0 Access Reset Bit 5 – ACMP0D: ACMP0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding analog pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
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25. DAC – Digital to Analog Converter 25.1. Features • • • • • • 25.2. 10-bits resolution 8-bits linearity ±0.5LSB accuracy between 100mV and AVCC - 100mV Vout = DAC × VREF/1023 The DAC could be connected to the negative inputs of the analog comparators and/or to a dedicated output driver The output impedance of the driver is around 100Ohm.
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Figure 25-1. Digital to analog converter block schematic DAC re s ult D2A pin Vre f DAC Output drive r 10 1 0 10 10 DAC High bits DAC Low bits S ource s DACH Upda te DAC trigge r Edge de te ctor DAATE DACL DATS 2 DATS 1 DATS 0 - DALA DAOE DAEN DACON Related Links ADC Noise Canceler on page 310 Analog Input Circuitry on page 311 Analog Noise Canceling Techniques on page 311 Offset Compensation Schemes on page 312 ADC Accuracy Definitions on page 312 ADMUX on page 321 25.3.
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In order to have an accurate sampling frequency control, there is the possibility to update the DAC input values through different trigger events. 25.4. Starting a conversion The DAC is configured thanks to the DACON register. As soon as the DAEN bit in DACON register is set, the DAC converts the value present on the DACH and DACL registers in accordance with the register DACON setting. Alternatively, a conversion can be triggered automatically by various sources.
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25.5.1. Digital to Analog Conversion Control Register Name: DACON Offset: 0x90 Reset: 0x0 Property: R/W Bit 7 6 DAATE 5 4 3 DATS[2:0] 2 1 0 DALA DAOE DAEN 0 0 0 Access Reset 0 0 0 0 Bit 7 – DAATE: DAC Auto Trigger Enable Set this bit to update the DAC input value on the positive edge of the trigger signal selected with the DACTS2-0 bit in DACON register. Clear it to automatically update the DAC input when a value is written on DACH register.
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25.5.2. Digital to Analog Converter input Register DACH and DACL registers contain the value to be converted into analog voltage. Writing the DACL register prohibits the update of the input value until DACH has not been written too. So the normal way to write a 10-bit value in the DAC register is firstly to write DACL the DACH. In order to work easily with only eight bits, there is the possibility to left adjust the input value. Like this it is sufficient to write DACH to update the DAC value.
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26. DBG - debugWIRE On-chip Debug System 26.1. Features • • • • • • • • • • 26.2.
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The debugWIRE Setup shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • 26.4. • Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ.
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26.6.1. debugWire Data Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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27. BTLDR - Boot Loader Support – Read-While-Write Self-Programming 27.1. Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 1. A page is a section in the Flash consisting of several bytes (see Table. No. of Words in a Page and No.
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27.4. Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section.
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Figure 27-1. Read-While-Write vs.
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Figure 27-2.
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• • • • To protect the entire Flash from a software update by the MCU To protect only the Boot Loader Flash section from a software update by the MCU To protect only the Application Flash section from a software update by the MCU Allow software update in the entire Flash The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only.
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can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code. The fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 27-4.
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Figure 27-3. Addressing the Flash During SPM BIT 15 ZPAGEMSB ZPCMSB 1 0 0 Z - REGISTER PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: The different variables used in this figure are listed in the Related Links. 27.8. Self-Programming the Flash The program memory is updated in a page by page fashion.
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can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. Please refer to Simple Assembly Code Example for a Boot Loader. 27.8.1. Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “0x0000011” to Store Program Memory Control and Status Register (SPMCSR) and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
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busy. During Self-Programming the Interrupt Vector table should be moved to the BLS as described in Watchdog Timer chapter, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the SPMCSR.RWWSB by writing the SPMCSR.RWWSRE. Please refer to Simple Assembly Code Example for a Boot Loader for an example. Related Links Watchdog System Reset on page 69 27.8.7.
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Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the SPMCSR.BLBSET and SPMCSR.SPMEN are set, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 When reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the SPMCSR.
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1. 2. 3. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used.
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; re-enable the RWW section ldi spmcrval, (1<
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; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
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Table 27-7.
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Please refer to Addressing the Flash During Self-Programming for details about the use of Z-pointer during Self- Programming. 27.8.15. ATmega32M1 Boot Loader Parameters The following tables are the parameters used in the description of the self programming are given. Table 27-10.
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Variable Corresponding Description Z-value(1) PCPAGE PC[13:6] Z14:Z7 Program counter page address: Page select, for page erase and page write PCWORD PC[5:0] Program counter word address: Word select, for filling temporary buffer (must be zero during page write operation) Z6:Z1 Note: 1. Z15:Z13: always ignored Z0: should be zero for all SPM commands, byte select for the LPM instruction.
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Table 27-15. Explanation of Different Variables used in Figure 27-3 Variable Corresponding Description Z-value(1) PCMSB 14 Most significant bit in the Program Counter. (The Program Counter is 15 bits PC[14:0]) PAGEMSB 7 Most significant bit which is used to address the words within one page (64 words in a page requires 7 bits PC [5:0]). ZPCMSB Z15 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
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27.9.1. SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations. When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Register (SPMCSR.BLBSET and SPMCSR.SPMEN), will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. Please refer to Reading the Fuse and Lock Bits from Software in this chapter.
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28. MEMPROG- Memory Programming 28.1. Program And Data Memory Lock Bits The devices provides six Lock bits. These can be left unprogrammed ('1') or can be programmed ('0') to obtain the additional features listed in Table. Lock Bit Protection Modes in this section. The Lock bits can only be erased to “1” with the Chip Erase command. Table 28-1. Lock Bit Byte(1) Lock Bit Byte Bit No.
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Table 28-3. Lock Bit Protection - BLB0 Mode(1)(2). BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or Load Program Memory (LPM) instruction accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
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Extended Fuse Byte Bit No.
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PSCRB PSCARV PSCBRV PSCOUTnA PSCOUTnB BODLEVEL2 (1) 2 Brown-out detector 1 (unprogrammed) trigger level BODLEVEL1 (1) 1 Brown-out detector 1 (unprogrammed) trigger level BODLEVEL0 (1) 0 Brown-out detector 1 (unprogrammed) trigger level Table 28-7. Fuse High byte High Fuse byte Bit no.
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1. 2. 3. 4. Note: The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 8-9 on page 31 for details. Note: The default setting of CKSEL3..0 results in internal RC Oscillator @ 8MHz. See Table 8-9 on page 31 for details. Note: The CKOUT Fuse allows the system clock to be output on PORTB0. See “Clock output buffer” on page 32 for details. Note: See “System clock prescaler” on page 32 for details. The status of the Fuse bits is not affected by Chip Erase.
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28.6. Page Size Table 28-10. No. of Words in a Page and No. of Pages in the Flash Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATmega16M1 8K words (16Kbytes) 64 words PC[5:0] 128 PC[12:6] 12 ATmega32M1 16K words (32Kbytes) 64 words PC[5:0] 256 PC[13:6] 13 ATmega64M1 32K words (64Kbytes) 128 words PC[6:0] 256 PC[14:7] 14 Table 28-11. No. of Words in a Page and No. of Pages in the EEPROM 28.7. Device EEPROM Size Page Size PCWORD No.
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Figure 28-1. Parallel Programming +4.5 - 5.5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12V BS2 VCC +4.5 - 5.5V AVCC PC[1:0]:PB[5:0] DATA RESET PC2 XTAL1 GND Note: VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 4.5 - 5.5V Table 28-12.
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Table 28-14. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1) 0 1 Load Data (High or Low data byte for Flash determined by BS1) 1 0 Load Command 1 1 No Action, Idle Table 28-15.
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4. 5. 6. 28.8.2. Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. • • • 28.8.3. Keep the Prog_enable pins unchanged for at least 10μs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. Wait until VCC actually reaches 4.5 - 5.5V before giving any parallel programming commands.
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Step C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. Step D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. Step E. Latch Data 1. Set BS1 to “1”. This selects high data byte. 2. Give PAGEL a positive pulse.
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Figure 28-2. Addressing the Flash Which Is Organized in Pages PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: PCPAGE and PCWORD are listed in the table of No. of Words in a Page and No. of Pages in the Flash in Page Size section. Programming the Flash Waveforms F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR.
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1. 2. 3. 4. 5. 6. 7. Step A: Load Command “0001 0001”. Step G: Load Address High Byte (0x00 - 0xFF). Step B: Load Address Low Byte (0x00 - 0xFF). Step C: Load Data (0x00 - 0xFF). Step E: Latch data (give PAGEL a positive pulse). Step K:Repeat 3 through 5 until the entire buffer is filled. Step L: Program EEPROM page 7.1. Set BS1 to “0”. 7.2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.
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4. 5. 28.8.8. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. Set OE to “1”. Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (Please refer to Programming the Flash for details on Command and Data loading): 1. 2. 3. 28.8.9. Step A: Load Command “0100 0000”. Step C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. Give WR a negative pulse and wait for RDY/BSY to go high.
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28.8.11. Programming the Lock Bits The algorithm for programming the Lock bits is as follows (Please refer to Programming the Flash for details on Command and Data loading): 1. 2. 3. Step A: Load Command “0010 0000”. Step C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. Give WR a negative pulse and wait for RDY/BSY to go high.
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28.8.14. Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (Please refer to Programming the Flash for details on Command and Address loading): 1. 2. 3. 4. Step A: Load Command “0000 1000”. Step B: Load Address Low Byte, 0x00. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. Set OE to “1”. 28.8.15. Parallel Programming Characteristics For characteristics of the Parallel Programming, please refer to Parallel Programming Characteristics.
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28.9.1. Serial Programming Pin Mapping Table 28-16. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB3 I Serial Data in MISO PB4 O Serial Data out SCK PB5 I Serial Clock Note: The pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. 28.9.2. Serial Programming Algorithm When writing serial data to the device, data is clocked on the rising edge of SCK.
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6. 7. 8. tWD_EEPROM before issuing the next byte. In a chip erased device, no 0xFF in the data file(s) need to be programmed. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. At the end of the programming session, RESET can be set high to commence normal operation. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 28-17.
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Instruction/Operation Instruction Format Byte 1 Byte 2 Byte 3 Byte 4 Read Extended Fuse Bits 0x50 0x08 0x00 data byte out Read Calibration Byte 0x38 0x00 0x00 data byte out Write Program Memory Page 0x4C adr MSB(8) adr LSB(8) 0x00 Write EEPROM Memory 0xC0 0000 00aa aaaa aaaa data byte in Write EEPROM Memory Page (page access) 0xC2 0000 00aa aaaa aa00 0x00 Write Lock bits 0xAC 0xE0 0x00 data byte in Write Fuse bits 0xAC 0xA0 0x00 data byte in Write Fuse High bits 0xAC 0x
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Figure 28-7. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Adr MSB Bit 15 B Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr LSB Adr MSB Byte 3 Adr LSB Bit 15 B 0 Byte 4 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 28.9.4. SPI Serial Programming Characteristics Figure 28-8.
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29. Electrical characteristics 29.1. Absolute Maximum Ratings* Operating temperature -40°C to +85°C Storage temperature -65°C to +150°C Voltage on any pin except RESET with respect to ground -0.5V to VCC +0.5V Voltage on RESET with respect to ground -0.5V to +13.0V Maximum operating voltage 6.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
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29.2. DC characteristics Table 29-1. TA = -40°C to +85°C, VCC = 2.7V to 5.5V (unless otherwise noted). Symbol Parameter Condition Min. VIL Input Low Voltage Port B, C & D and XTAL1, XTAL2 pins as I/O VIH Input High Voltage Port B, C & D and XTAL1, XTAL2 pins as I/O VIL1 Input Low Voltage XTAL1 pin , external -0.5 clock selected 0.1VCC (1) VIH1 Input High Voltage XTAL1 pin , external 0.7VCC (2) clock selected VCC+0.5 VIL2 Input Low Voltage RESET pin -0.5 0.
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Symbol Parameter Condition Min. Typ. Max. Units kΩ RRST Reset Pull-up Resistor 30 200 Rpu I/O Pin Pull-up Resistor 20 50 ICC Power Supply Current Power-down mode (5) Vhysr Analog Comparator Hysteresis Voltage Active 8MHz, VCC = 3V, RC osc, PRR = 0xFF 3.8 8 Active 16MHz, VCC = 5V, Ext Clock, PRR = 0xFF 14 30 Idle 8MHz, VCC = 3V, RC Osc 1.5 4 Idle 16MHz, VCC = 5V, Ext Clock 5.
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1] The sum of all IOL, for ports B0 - B1, C2 - C3, D4, E1 - E2 should not exceed 70mA 2] The sum of all IOL, for ports B6 - B7, C0 - C1, D0 -D3, E0 should not exceed 70mA 3] The sum of all IOL, for ports B2 - B5, C4 - C7, D5 - D7 should not exceed 70mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.
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29.4. Clock characteristics 29.4.1. Calibrated internal RC oscillator accuracy Table 29-2. Calibration accuracy of internal RC oscillator. Factory calibration User calibration 29.5. Frequency VCC 8.0MHz 3V 7.3MHz - 8.1MHz Temperature Calibration accuracy 25°C ±1%  2.7V - 5.5V  -40°C to +85°C  ±10% External clock drive characteristics Figure 29-2. External clock drive waveforms. VIH1 VIL1 Table 29-3. External clock drive. Symbol  Parameter VCC = 2.7V - 5.5V VCC = 4.5V - 5.
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29.6. System and reset characteristics Table 29-4. Reset, brown-out (1) and internal voltage (1) characteristics. Symbol Parameter Min Typ Max Units VPOT Power-on Reset Threshold Voltage (rising) 1.1 1.4 1.7 V Power-on Reset Threshold Voltage (falling)(2) 0.8 0.9 1.6 VPORMAX VCC maximum start voltage to ensure internal Power-on Reset signal VPORMIN VCC minimum start voltage to ensure internal Power-on Reset signal -0.1 VCCRR VCC Rise Rate to ensure Power-on Reset 0.
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29.7. PLL characteristics Table 29-6. PLL characteristics - VCC = 2.7V to 5.5V (unless otherwise noted). Symbol Parameter Min. Typ. Max. Units PLLIF Input frequency 0.5 1 2 MHz PLLF PLL factor PLLLT Lock-in time 64 µS 64 Note: While connected to external clock or external oscillator, PLL Input Frequency must be selected to provide outputs with frequency in accordance with driven parts of the circuit (CPU core, PSC...). 29.8.
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Note: In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK <12MHz - 3 tCLCL for fCK >12MHz Figure 29-3. SPI interface timing requirements (Master mode). SS 6 1 S CK (CP OL = 0) 2 2 S CK (CP OL = 1) 4 MIS O (Da ta Input) 5 3 MS B ... LS B 7 MOS I (Da ta Output) MS B 8 LS B ... Figure 29-4. SPI interface timing requirements (Slave mode). SS 10 9 16 S CK (CP OL = 0) 11 11 S CK (CP OL = 1) 13 MOS I (Da ta Input) 14 12 MS B ...
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29.9. ADC characteristics Table 29-8. ADC characteristics - TA = -40°C to +85°C, VCC = 2.7V to 5.5V (unless otherwise noted). Symb ol TUE INL DNL Parameter Condition Resolution Single Ended Conversion 10 Absolute accuracy VCC = 5V, VREF = 2.56V, ADC clock = 1MHz 3.2 5.0 VCC = 5V, VREF = 2.56V, ADC clock = 2MHz 3.2 5.0 Integral nonlinearity VCC = 5V, VREF = 2.56V, ADC clock = 1MHz 0.7 1.5 VCC = 5V, VREF = 2.56V, ADC clock = 2MHz 0.8 2.0 Differential nonlinearity VCC = 5V, VREF = 2.
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Symb ol Parameter Condition TUE Absolute accuracy Gain = 5×, 10×, VCC = 5V, VREF = 2.56V, ADC clock = 2MHz 1.5 3.5 Gain = 20×, VCC = 5V, VREF = 2.56V, ADC clock = 2MHz 1.5 4.0 Gain = 40×, VCC = 5V, VREF = 2.56V, ADC clock = 2MHz 1.5 4.5 Gain = 5×, 10×, VCC = 5V, VREF = 2.56V, ADC clock = 2MHz 0.1 1.5 Gain = 20×, VCC = 5V, VREF = 2.56V, ADC clock = 2MHz 0.2 2.5 Gain = 40×, VCC = 5V, VREF = 2.56V, ADC clock = 1MHz 0.3 3.5 Gain = 40×, VCC = 5V, VREF = 2.56V, ADC clock = 2MHz 0.7 4.
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29.10. Parallel Programming Characteristics Figure 29-5. Parallel programming timing, including some general timing requirements. tXLWL tXHXL XTAL1 tDVXH Data and control (DATA, XA0/1, BS1, BS2) tXLDX tP LBX t BVWL tBVP H PAGEL tWLBX tP HP L tWLWH WR tP LWL WLRL RDY/BSY tWLRH Figure 29-6. Parallel programming timing, loading sequence with timing requirements.
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Note: The timing requirements shown in the figures above (that is, tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 29-9. Parallel programming characteristics, VCC = 5V ±10%. Symbol Parameter Min. VPP Programming Enable Voltage 11.
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30. Typical characteristics 30.1. Pin pull-up Figure 30-1. I/O pin pull-up resistor current versus input voltage. VCC = 5V. 140 120 IOP [µA] 100 80 60 40 20 -40°C 85°C 25°C 5.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VOP [V] Figure 30-2. I/O pin pull-up resistor current versus input voltage. VCC = 2.7V. 80 70 IOP [µA] 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 -40°C 85°C 25°C 2.
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Pin driver strength Figure 30-3. I/O pin low output voltage versus sink current. VCC = 5V. 1.0 85°C 0.9 0.8 25°C 0.7 -40°C VOL [V] 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 I OL [mA] 12 14 16 18 20 Figure 30-4. I/O pin low output voltage versus sink current. VCC = 3V. 0.7 85°C 0.6 25°C VOL [V] 0.5 -40°C 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [V] Figure 30-5. I/O pin output voltage versus source current. VCC = 5V. VOH [V] 30.2. 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.
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Figure 30-6. I/O pin output voltage versus source current. VCC = 3V. 3.0 2.9 VOH [V] 2.8 2.7 2.6 2.5 -40°C 2.4 25°C 2.3 85°C 2.2 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Pin Thresholds and Hysteresis Figure 30-7. I/O pin input threshold voltage versus VCC. VIH, I/O pin read as '1'. 3.0 85°C 25°C -40°C 2.8 Thre s hold [V] 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-8. I/O pin input threshold voltage versus VCC. VIL, I/O pin read as '0'. 2.
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Figure 30-9. I/O pin input hysteresis versus VCC. 0.45 85°C 25°C -40°C Input hys te re s is [mV] 0.43 0.41 0.39 0.37 0.35 0.33 0.31 0.29 0.27 0.25 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-10. Reset input threshold voltage versus VCC. VIH, I/O pin read as '1'. 2.4 85°C 25°C -40°C 2.2 Thre s hold [V] 2.0 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-11. Reset input threshold voltage versus VCC. VIL, I/O pin read as '0'. -40°C 85°C 25°C 2.4 Thre s hold [V] 2.
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Figure 30-12. Reset pull-up resistor current versus reset pin voltage. VCC = 5V. 120 100 IRES ET [µA] 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 85°C -40°C 25°C 5.0 4.5 VRES ET [V] Figure 30-13. Reset pull-up resistor current versus reset pin voltage. VCC = 2.7V. 60 50 IRES ET [µA] 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 85°C -40°C 25°C 2.6 VRES ET [V] Figure 30-14. XTAL1 input threshold voltage versus VCC. VIL, XTAL1 pin read as '0'. 2.
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Figure 30-15. XTAL1 input threshold voltage versus VCC. VIL, XTAL1 pin read as '1'. 4.0 -40°C 25°C 85°C Thre s hold [V] 3.5 3.0 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 30.4. BOD Thresholds and Analog Comparator Hysteresis Figure 30-16. BOD thresholds versus temperature. BODLEVEL is 2.7V. 2.800 1 2.775 Thre s hold [V] 2.750 0 2.725 2.700 2.675 2.650 2.625 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Te mpe ra ture [°C] Internal Oscillator Speed Figure 30-17.
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Figure 30-18. Watchdog oscillator frequency versus temperature. 130 129 Fre que ncy [kHz] 128 127 126 125 124 123 2.7 V 122 3.3 4.0 4.5 5.0 5.5 121 120 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 V V V V V 90 Te mpe ra ture [°C] Figure 30-19. Calibrated 8MHz oscillator frequency versus VCC. 8.15 85°C Fre que ncy [MHz] 8.10 25°C 8.05 8.00 7.95 -40°C 7.90 7.85 7.80 7.75 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 30-20. Calibrated 8MHz oscillator frequency versus osccal value.
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30.6. Using the Power Reduction Register The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. Table 30-1. Additional current consumption (percentage) in active and idle mode. Typical ICC [µA]. Percent of added consumption VCC = 5.0V, 16Mhz VCC = 3.0V, 8Mhz PRCAN 13 12 PRPSC 8 7.
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31. Register Summary Offset Name Bit Pos.
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Offset Name Bit Pos. 0x50 ACSR 7:0 0x51 DWDR 7:0 0x52 Reserved AC3IF AC2IF AC1IF AC0IF AC3O AC2O AC1O AC0O DWDR[7:0] 0x53 SMCR 7:0 SM2 SM1 SM0 SE 0x54 MCUSR 7:0 WDRF BORF EXTRF PORF 0x55 MCUCR 7:0 SPIPS IVSEL IVCE 0x56 Reserved 0x57 SPMCSR 7:0 SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN 7:0 SP7 SP6 SP5 SP4 SP3 PUD 0x58 ...
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Offset Name Bit Pos. 0x82 TCCR1C 7:0 0x83 Reserved 0x84 TCNT1L and 7:0 TCNT1[7:0] 0x85 TCNT1H 15:8 TCNT1[15:8] 7:0 ICR1[7:0] 0x86 0x87 ICR1L and ICR1H FOC1A FOC1B 15:8 ICR1[15:8] 0x88 OCR1AL and 7:0 OCR1A[7:0] 0x89 OCR1AH 15:8 OCR1A[15:8] 0x8A OCR1BL and 7:0 OCR1B[7:0] 0x8B OCR1BH 15:8 OCR1B[15:8] 0x8C ...
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Offset Name Bit Pos. 0xB7 PCTL 7:0 0xB8 PMIC0 7:0 POVENm PISELm PELEVm PFLTEm PAOCm PRFMm[2:0] 0xB9 PMIC1 7:0 POVENm PISELm PELEVm PFLTEm PAOCm PRFMm[2:0] 0xBA PMIC2 7:0 POVENm PISELm PELEVm PFLTEm PAOCm 0xBB PIM 7:0 PEVE2 PEVE1 PEVE PEOPE 0xBC PIFR 7:0 PEV2 PEV1 PEV PEOP PPRE[1:0] PCLKSEL PCCYC PRUN PRFMm[2:0] 0xBD ...
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Offset Name Bit Pos.
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32. Instruction Set Summary Table 31-1.
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Mnemonic Operands ICALL Description Flags #Clocks AVR None 3 / 4(1) PC(15:0) ← Z PC(21:16) ← 0 call Subroutine PC ← k None 4 / 5(1) RET Subroutine Return PC ← STACK None 4 / 5(1) RETI Interrupt Return PC ← STACK I 4 / 5(1) if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CALL Indirect Call to (Z) Op k CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register Cleared if (
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Flags #Clocks AVR (X) None 2(1) ← (X) None 2(1) X ← X+1 X ← X-1 None 2(1) Rd ← (X) Mnemonic Operands Description LD Rd, X Load Indirect Rd ← LD Rd, X+ Load Indirect and Post-Increment Rd LD Rd, -X Load Indirect and Pre-Decrement Op LD Rd, Y Load Indirect Rd ← (Y) None 2(1) LD Rd, Y+ Load Indirect and Post-Increment Rd ← (Y) None 2(1) Y ← Y+1 Y ← Y-1 None 2(1) Rd ← (Y) LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with
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Mnemonic Operands Description IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd Pop Register from Stack Op Flags #Clocks AVR Rd ← I/O(A) None 1 I/O(A) ← Rr None 1 STACK ← Rr None 2 Rd ← STACK None 2 Flags #Clocks AVR Table 31-4.
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Mnemonic Operands Description Op #Clocks AVR Flags SEH Set Half Carry Flag in SREG H ← 1 H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 Table 31-5. MCU Control Instructions Mnemonic Operands Description BREAK Break NOP No Operation SLEEP Sleep WDR Watchdog Reset Operation Flags #Clocks AVR (See also in Debug interface description) None 1 None 1 (see also power management and sleep description) None 1 (see also Watchdog Controller description) None 1 Note: 1.
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33. Errata 33.1. Errata ATmega16M1 The revision letter in this section refers to revisions of the ATmega16M1 device. Rev. A 33.2. Not Sampled. Errata ATmega32M1 The revision letter in this section refers to revisions of the ATmega32M1 device. Rev. A 33.3. Not Sampled. Errata ATmega64M1 The revision letter in this section refers to revisions of the ATmega64M1 device. Rev. A Not Sampled.
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34. Packaging Information 34.1. 32-pin 32A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° L A1 A2 A COMMON DIMENSIONS (Unit of measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.
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34.2. PV 32 QFN PV, 32 - lead 7.0mm x 7.0mm body, 0.
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35. Datasheet revision history Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 35.1. 8209F – 10/2016 1. 35.2. 35.3. 35.4. 35.5. Content editing updates 8209E – 11/2012 1. Electrical characteristics added 2. Updated the whole content with Atmel new logo 3. Content editing updates 8209D – 11/10 1. Updated footnote 1in “Features” on page 1. 2.
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35.6. 8209A – 08/09 1. Initial revision.
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