Datasheet

ATmega32A

 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 91

Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sam-

pling. The external clock must be ensured to have less than half the system clock frequency (f

ExtClk

< f

clk_I/O

/2) given

a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can

detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock

frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recom-

mended that maximum frequency of an external clock source is less than f

clk_I/O

/2.5.

An external clock source can not be prescaled.

Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1

(1)

Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 16-1.

PSR10

Clear

clk

I/O

Synchronization