Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 7
ATmega32A
23.5 Prescaling and Conversion Timing................................................................ 204
23.6 Changing Channel or Reference Selection ................................................... 207
23.7 ADC Noise Canceler ..................................................................................... 208
23.8 ADC Conversion Result................................................................................. 212
23.9 Register Description ...................................................................................... 214
24 JTAG Interface and On-chip Debug System ...................................... 218
24.1 Features ........................................................................................................ 218
24.2 Overview........................................................................................................ 218
24.3 TAP – Test Access Port ................................................................................ 218
24.4 TAP Controller ............................................................................................... 220
24.5 Using the Boundary-scan Chain.................................................................... 221
24.6 Using the On-chip Debug System ................................................................. 221
24.7 On-chip Debug Specific JTAG Instructions ................................................... 222
24.8 Using the JTAG Programming Capabilities ................................................... 222
24.9 Register Description ...................................................................................... 223
24.10 Bibliography................................................................................................... 223
25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 224
25.1 Features ........................................................................................................ 224
25.2 Overview........................................................................................................ 224
25.3 Data Registers............................................................................................... 224
25.4 Boundary-scan Specific JTAG Instructions ................................................... 226
25.5 Boundary-scan Chain .................................................................................... 227
25.6 ATmega32A Boundary-scan Order ............................................................... 237
25.7 Boundary-scan Description Language Files.................................................. 242
25.8 Register Description ...................................................................................... 242
26 Boot Loader Support – Read-While-Write Self-Programming ......... 243
26.1 Features ........................................................................................................ 243
26.2 Overview........................................................................................................ 243
26.3 Application and Boot Loader Flash Sections................................................. 243
26.4 Read-While-Write and no Read-While-Write Flash Sections ........................ 243
26.5 Boot Loader Lock Bits ................................................................................... 246
26.6 Entering the Boot Loader Program................................................................ 247
26.7 Addressing the Flash during Self-Programming............................................ 248
26.8 Self-Programming the Flash.......................................................................... 249
26.9 Register Description ...................................................................................... 254