Datasheet

ATmega32A
 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 65
OC0, Output Compare Match output: The PB3 pin can serve as an external output for the Timer/Counter0 Com-
pare Match. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC0 pin is
also the output pin for the PWM mode timer function.
• AIN0/INT2 – Port B, Bit 2
AIN0, Analog Comparator Positive input. Configure the port pin as input with the internal pull-up switched off to
avoid the digital port function from interfering with the function of the Analog Comparator.
INT2, External Interrupt Source 2: The PB2 pin can serve as an external interrupt source to the MCU.
• T1 – Port B, Bit 1
T1, Timer/Counter1 Counter Source.
• T0/XCK – Port B, Bit 0
T0, Timer/Counter0 Counter Source.
XCK, USART External Clock. The Data Direction Register (DDB0) controls whether the clock is output (DDB0 set)
or input (DDB0 cleared). The XCK pin is active only when the USART operates in Synchronous mode.
Table 13-7 and Table 13-8 relate the alternate functions of Port B to the overriding signals shown in Figure 13-5 on
page 61. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI
MSTR OUTPUT and SPI SLAVE INPUT.
Table 13-7. Overriding Signals for Alternate Functions in PB7:PB4
Signal
Name PB7/SCK PB6/MISO PB5/MOSI PB4/SS
PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
PUOV PORTB7 • PUD PORTB6 • PUD PORTB5 • PUD PORTB4 • PUD
DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
DDOV 0 0 0 0
PVOE SPE • MSTR SPE • MSTR
SPE • MSTR 0
PVOV SCK OUTPUT SPI SLAVE OUTPUT SPI MSTR OUTPUT 0
DIEOE 0 0 0 0
DIEOV 0 0 0 0
DI SCK INPUT SPI MSTR INPUT SPI SLAVE INPUT SPI SS
AIO – – – –