Datasheet

ATmega32A

 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 26

8.4.3 Preventing EEPROM Corruption

During periods of low V

CC,

the EEPROM data can be corrupted because the supply voltage is too low for the CPU

and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and

the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write

sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute

instructions incorrectly, if the supply voltage is too low.

EPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by

enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the

needed detection level, an external low V

Reset Protection circuit can be used. If a reset occurs while a write

operation is in progress, the write operation will be completed provided that the power supply voltage is

sufficient.

8.5 I/O Memory

The I/O space definition of the AVR ATmega32A is shown in “Register Summary” on page 324.

All ATmega32A I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and

OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Reg-

isters within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the AVR

Instruction Set Manual on www.microchip.com. When using the I/O specific commands IN and OUT, the I/O

addresses $00 - $3F must be used. When addressing I/O Registers as data space using LD and ST instructions,

$20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory

addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will

operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI

and SBI instructions work with registers $00 to $1F only.

The I/O and Peripherals Control Registers are explained in later sections.