Datasheet

ATmega32A
 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 222
The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must
be programmed and no Lock bits must be set for the On-chip Debug system to work. As a security feature, the On-
chip Debug system is disabled when any Lock bits are set. Otherwise, the On-chip Debug system would have pro-
vided a back-door into a secured device.
The AVR JTAG ICE is a powerful development tool for On-chip Debugging of all AVR 8-bit RISC Microcontrollers
with IEEE 1149.1 compliant JTAG interface. The JTAG ICE and the Atmel Studio user interface give the user com-
plete control of the internal resources of the microcontroller, helping to reduce development time by making
debugging easier. The JTAG ICE performs real-time emulation of the micrcontroller while it is running in a target
system.
Refer to the Support Tools section on the AVR pages on www.microchip.com for a full description of the AVR
JTEG ICE. Atmel Studio can be downloaded free from Software section on the same web site.
All necessary execution commands are available in Atmel Studio, both on source level and on disassembly level.
The user can execute the program, single step through the code either by tracing into or stepping over functions,
step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execu-
tion, and reset the execution target. In addition, the user can have an unlimited number of code breakpoints (using
the BREAK instruction) and up to two data memory breakpoints, alternatively combined as a mask (range) Break
Point.
24.7 On-chip Debug Specific JTAG Instructions
The On-chip Debug support is considered being private JTAG instructions, and distributed within Microchip and to
selected third party vendors only. Instruction opcodes are listed for reference.
24.7.1 PRIVATE0; $8
Private JTAG instruction for accessing On-chip Debug system.
24.7.2 PRIVATE1; $9
Private JTAG instruction for accessing On-chip Debug system.
24.7.3 PRIVATE2; $A
Private JTAG instruction for accessing On-chip Debug system.
24.7.4 PRIVATE3; $B
Private JTAG instruction for accessing On-chip Debug system.
24.8 Using the JTAG Programming Capabilities
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI and TDO. These are
the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not
required to apply 12V externally. The JTAGEN fuse must be programmed and the JTD bit in the MCUSR Register
must be cleared to enable the JTAG Test Access Port.
The JTAG programming capability supports:
• Flash programming and verifying
• EEPROM programming and verifying
• Fuse programming and verifying
• Lock bit programming and verifying
The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are programmed, the
OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no
back-door exists for reading out the content of a secured device.