Datasheet

ATmega32A

 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 136

19. SPI – Serial Peripheral Interface

19.1 Features

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

19.2 Overview

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32A and

peripheral devices or between several AVR devices.

Figure 19-1. SPI Block Diagram

(1)

Note: 1. Refer to Figure 1-1 on page 10, and Table 13-6 on page 64 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2. The system consists of two

Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low

the Slave Select SS

pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift

SPI2X

DIVIDER

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