Datasheet

T1, Timer/Counter1 Counter Source.
• T0/XCK – Port B, Bit 0
T0, Timer/Counter0 Counter Source.
XCK, USART External Clock. The Data Direction Register (DDB0) controls whether the clock is output
(DDB0 set) or input (DDB0 cleared). The XCK pin is active only when the USART operates in
Synchronous mode.
The tables below relate the alternate functions of Port B to the overriding signals shown in the figure in
section Alternate Port Functions. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal,
while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 17-7. Overriding Signals for Alternate Functions in PB7:PB4
Signal
Name
PB7/SCK PB6/MISO PB5/MOSI PB4/SS
PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
PUOV PORTB7 • PUD PORTB6 • PUD PORTB5 • PUD PORTB4 • PUD
DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR
DDOV 0 0 0 0
PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0
PVOV SCK OUTPUT SPI SLAVE OUTPUT SPI MSTR OUTPUT 0
DIEOE 0 0 0 0
DIEOV 0 0 0 0
DI SCK INPUT SPI MSTR INPUT SPI SLAVE INPUT SPI SS
AIO – – – –
Table 17-8. Overriding Signals for Alternate Functions in PB3:PB0
Signal
Name
PB3/OC0/AIN1 PB2/INT2/AIN0 PB1/T1 PB0/T0/XCK
PUOE 0 0 0 0
PUOV 0 0 0 0
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE OC0 ENABLE 0 0 UMSEL
PVOV OC0 0 0 XCK OUTPUT
DIEOE 0 INT2 ENABLE 0 0
DIEOV 0 1 0 0
DI - INT2 INPUT T1 INPUT XCK INPUT/T0 INPUT
AIO AIN1 INPUT AIN0 INPUT – –
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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