Datasheet

14.5.1. MCUCSR – MCU Control and Status Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
Name: MCUCSR
Offset: 0x34
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x54
Bit 7 6 5 4 3 2 1 0
JTRF WDRF BORF EXTRF PORF
Access
R/W R/W R/W R/W R/W
Reset - - - - -
Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG
instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
to the flag.
Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
to the flag.
Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero
to the flag.
Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make
use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as
early as possible in the program. If the register is cleared before another reset occurs, the source of the
reset can be found by examining the Reset Flags.
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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