Datasheet

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Table Of Contents

Introduction
Features
Table of Contents
1. Description
2. Configuration Summary
3. Ordering Information
4. Block Diagram
5. Pin Configurations
- 5.1. VCC
- 5.2. GND
- 5.3. PortA (PA7:PA0)
- 5.4. Port B (PB7:PB0)
- 5.5. Port C (PC7:PC0)
- 5.6. Port D (PD7:PD0)
- 5.7. RESET
- 5.8. XTAL1
- 5.9. XTAL2
- 5.10. AVCC
- 5.11. AREF
6. Resources
7. Data Retention
8. About Code Examples
9. Capacitive Touch Sensing
10. AVR CPU Core
- 10.1. Overview
- 10.2. ALU – Arithmetic Logic Unit
- 10.3. Status Register
  - 10.3.1. SREG – The AVR Status Register
- 10.4. General Purpose Register File
  - 10.4.1. The X-register, Y-register and Z-register
- 10.5. Stack Pointer
- 10.6. Instruction Execution Timing
- 10.7. Reset and Interrupt Handling
  - 10.7.1. Interrupt Response Time
11. AVR Memories
- 11.1. Overview
- 11.2. In-System Reprogrammable Flash Program Memory
- 11.3. SRAM Data Memory
  - 11.3.1. Data Memory Access Times
- 11.4. EEPROM Data Memory
- 11.5. I/O Memory
- 11.6. Register Description
12. System Clock and Clock Options
- 12.1. Clock Systems and their Distribution
- 12.2. Clock Sources
- 12.3. Default Clock Source
- 12.4. Crystal Oscillator
- 12.5. Low-frequency Crystal Oscillator
- 12.6. External RC Oscillator
- 12.7. Calibrated Internal RC Oscillator
- 12.8. External Clock
- 12.9. Timer/Counter Oscillator
- 12.10. Register Description
  - 12.10.1. OSCCAL – The Oscillator Calibration Register
13. Power Management and Sleep Modes
- 13.1. Sleep Modes
- 13.2. Idle Mode
- 13.3. ADC Noise Reduction Mode
- 13.4. Power-down Mode
- 13.5. Power-save Mode
- 13.6. Standby Mode
- 13.7. Extended Standby Mode
- 13.8. Minimizing Power Consumption
- 13.9. Register Description
  - 13.9.1. MCUCR – MCU Control Register
14. System Control and Reset
- 14.1. Resetting the AVR
- 14.2. Reset Sources
- 14.3. Internal Voltage Reference
  - 14.3.1. Voltage Reference Enable Signals and Start-up Time
- 14.4. Watchdog Timer
- 14.5. Register Description
  - 14.5.1. MCUCSR – MCU Control and Status Register
  - 14.5.2. WDTCR – Watchdog Timer Control Register
15. Interrupts
- 15.1. Interrupt Vectors in ATmega32A
  - 15.1.1. Moving Interrupts Between Application and Boot Space
- 15.2. Register Description
  - 15.2.1. GICR – General Interrupt Control Register
16. External Interrupts
- 16.1. Register Description
17. I/O Ports
- 17.1. Overview
- 17.2. Ports as General Digital I/O
- 17.3. Alternate Port Functions
- 17.4. Register Description
18. Timer/Counter0 and Timer/Counter1 Prescalers
- 18.1. Overview
- 18.2. Internal Clock Source
- 18.3. Prescaler Reset
- 18.4. External Clock Source
- 18.5. Register Description
  - 18.5.1. SFIOR – Special Function IO Register
19. 16-bit Timer/Counter1
- 19.1. Features
- 19.2. Overview
- 19.3. Accessing 16-bit Registers
  - 19.3.1. Reusing the Temporary High Byte Register
- 19.4. Timer/Counter Clock Sources
- 19.5. Counter Unit
- 19.6. Input Capture Unit
- 19.7. Output Compare Units
- 19.8. Compare Match Output Unit
  - 19.8.1. Compare Output Mode and Waveform Generation
- 19.9. Modes of Operation
- 19.10. Timer/Counter Timing Diagrams
- 19.11. Register Description
20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 20.1. Features
- 20.2. Overview
  - 20.2.1. Registers
  - 20.2.2. Definitions
- 20.3. Timer/Counter Clock Sources
- 20.4. Counter Unit
- 20.5. Output Compare Unit
- 20.6. Compare Match Output Unit
  - 20.6.1. Compare Output Mode and Waveform Generation
- 20.7. Modes of Operation
- 20.8. Timer/Counter Timing Diagrams
- 20.9. Asynchronous Operation of the Timer/Counter
  - 20.9.1. Asynchronous Operation of Timer/Counter2
- 20.10. Timer/Counter Prescaler
- 20.11. Register Description
21. 8-bit Timer/Counter0 with PWM
- 21.1. Features
- 21.2. Overview
  - 21.2.1. Registers
  - 21.2.2. Definitions
- 21.3. Timer/Counter Clock Sources
- 21.4. Counter Unit
- 21.5. Output Compare Unit
- 21.6. Compare Match Output Unit
  - 21.6.1. Compare Output Mode and Waveform Generation
- 21.7. Modes of Operation
- 21.8. Timer/Counter Timing Diagrams
- 21.9. Register Description
22. SPI – Serial Peripheral Interface
- 22.1. Features
- 22.2. Overview
- 22.3. SS Pin Functionality
  - 22.3.1. Slave Mode
  - 22.3.2. Master Mode
- 22.4. Data Modes
- 22.5. Register Description
23. USART - Universal Synchronous and Asynchronous serial Receiver and Transmitter
- 23.1. Features
- 23.2. Overview
  - 23.2.1. AVR USART vs. AVR UART – Compatibility
- 23.3. Clock Generation
- 23.4. Frame Formats
  - 23.4.1. Parity Bit Calculation
- 23.5. USART Initialization
- 23.6. Data Transmission – The USART Transmitter
- 23.7. Data Reception – The USART Receiver
- 23.8. Asynchronous Data Reception
- 23.9. Multi-Processor Communication Mode
  - 23.9.1. Using MPCM
- 23.10. Accessing UBRRH/UCSRC Registers
  - 23.10.1. Write Access
  - 23.10.2. Read Access
- 23.11. Register Description
- 23.12. Examples of Baud Rate Setting
24. TWI - Two-wire Serial Interface
- 24.1. Features
- 24.2. Overview
- 24.3. Two-Wire Serial Interface Bus Definition
  - 24.3.1. TWI Terminology
  - 24.3.2. Electrical Interconnection
- 24.4. Data Transfer and Frame Format
- 24.5. Multi-master Bus Systems, Arbitration and Synchronization
- 24.6. Using the TWI
- 24.7. Multi-master Systems and Arbitration
- 24.8. Register Description
25. AC - Analog Comparator
- 25.1. Overview
- 25.2. Analog Comparator Multiplexed Input
- 25.3. Register Description
  - 25.3.1. SFIOR – Analog Comparator Control and Status Register
  - 25.3.2. ACSR – Analog Comparator Control and Status Register
26. ADC - Analog to Digital Converter
- 26.1. Features
- 26.2. Overview
- 26.3. Starting a Conversion
- 26.4. Prescaling and Conversion Timing
  - 26.4.1. Differential Gain Channels
- 26.5. Changing Channel or Reference Selection
  - 26.5.1. ADC Input Channels
  - 26.5.2. ADC Voltage Reference
- 26.6. ADC Noise Canceler
- 26.7. ADC Conversion Result
- 26.8. Register Description
27. JTAG Interface and On-chip Debug System
- 27.1. Features
- 27.2. Overview
- 27.3. TAP – Test Access Port
- 27.4. TAP Controller
- 27.5. Using the Boundary-scan Chain
- 27.6. Using the On-chip Debug System
- 27.7. On-chip Debug Specific JTAG Instructions
- 27.8. Using the JTAG Programming Capabilities
- 27.9. Bibliography
- 27.10. IEEE 1149.1 (JTAG) Boundary-scan
  - 27.10.1. Features
  - 27.10.2. System Overview
- 27.11. Data Registers
- 27.12. Boundry-scan Specific JTAG Instructions
- 27.13. Boundary-scan Chain
- 27.14. ATmega32A Boundary-scan Order
- 27.15. Boundary-scan Description Language Files
- 27.16. Register Description
  - 27.16.1. OCDR – On-chip Debug Register
  - 27.16.2. MCUCSR – MCU Control and Status Register
28. BTLDR - Boot Loader Support – Read-While-Write Self-Programming
- 28.1. Features
- 28.2. Overview
- 28.3. Application and Boot Loader Flash Sections
  - 28.3.1. Application Section
  - 28.3.2. BLS – Boot Loader Section
- 28.4. Read-While-Write and No Read-While-Write Flash Sections
  - 28.4.1. RWW – Read-While-Write Section
  - 28.4.2. NRWW – No Read-While-Write Section
- 28.5. Boot Loader Lock Bits
- 28.6. Entering the Boot Loader Program
- 28.7. Addressing the Flash During Self-Programming
- 28.8. Self-Programming the Flash
- 28.9. Register Description
  - 28.9.1. SPMCR – Store Program Memory Control Register
29. Memory Programming
- 29.1. Program and Data Memory Lock Bits
- 29.2. Fuse Bits
  - 29.2.1. Latching of Fuses
- 29.3. Signature Bytes
- 29.4. Signature Bytes
- 29.5. Calibration Byte
- 29.6. Parallel Programming Parameters, Pin Mapping, and Commands
  - 29.6.1. Signal Names
- 29.7. Parallel Programming
- 29.8. Serial Downloading
- 29.9. Serial Programming Pin Mapping
- 29.10. Programming Via the JTAG Interface
30. Electrical Characteristics
- 30.1. DC Characteristics
- 30.2. Speed Grades
- 30.3. Clock Characteristics
  - 30.3.1. External Clock Drive Waveforms
  - 30.3.2. External Clock Drive
- 30.4. System and Reset Characteristics
- 30.5. Two-wire Serial Interface Characteristics
- 30.6. SPI Timing Characteristics
- 30.7. ADC Characteristics
31. Typical Characteristics
- 31.1. Active Supply Current
- 31.2. Idle Supply Current
- 31.3. Power-down Supply Current
- 31.4. Power-save Supply current
- 31.5. Standby Supply Current
- 31.6. Pin Pull-up
- 31.7. Pin Driver Strength
- 31.8. Pin Thresholds and Hysteresis
- 31.9. BOD Thresholds and Analog Comparator Offset
- 31.10. Internal Oscillator Speed
- 31.11. Current Consumption of Peripheral Units
- 31.12. Current Consumption in Reset and Reset Pulsewidth
32. Register Summary
33. Instruction Set Summary
34. Packaging Information
- 34.1. 44-pin TQFP
- 34.2. 40-pin PDIP
- 34.3. 44-pin VQFN
35. Errata
- 35.1. ATmega32A, rev. J to rev. K
- 35.2. ATmega32A, rev. G to rev. I
36. Datasheet Revision History
- 36.1. 8155I - 08/2016
- 36.2. 8155H - 08/2016
- 36.3. 8155G - 10/2015
- 36.4. 8155F - 08/2015
- 36.5. 8155E - 02/2014
- 36.6. 8155D – 10/2013
- 36.7. 8155C - 02/2011
- 36.8. 8155B – 07/2009
- 36.9. 8155A – 06/2008

12.1.3. Flash Clock – clk

FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously

with the CPU clock.

12.1.4. Asynchronous Timer Clock – clk

ASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an

external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time

counter even when the device is in sleep mode.

12.1.5. ADC Clock – clk

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order

to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

12.2. Clock Sources

The device has the following clock source options, selectable by Flash Fuse Bits as shown below. The

clock from the selected source is input to the AVR clock generator, and routed to the appropriate

modules.

Table 12-1. Device Clocking Options Select

Device Clocking Option CKSEL3:0

(1)

External Crystal/Ceramic Resonator 1111 - 1010

External Low-frequency Crystal 1001

External RC Oscillator 1000 - 0101

Calibrated Internal RC Oscillator 0100 - 0001

External Clock 0000

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU wakes up

from Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable

Oscillator operation before instruction execution starts. When the CPU starts from reset, there is as an

additional delay allowing the power to reach a stable level before commencing normal operation. The

Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT

Oscillator cycles used for each time-out is shown in the table below. The frequency of the Watchdog

Oscillator is voltage dependent as shown in Typical Characteristics.

Table 12-2. Number of Watchdog Oscillator Cycles

Typical Time-out (V

= 5.0V) Typical Time-out (V

= 3.0V) Number of Cycles

4.1ms 4.3ms 4K (4,096)

65ms 69ms 64K (65,536)