Datasheet

Symbol Parameter Condition Min Max Units
t
BUF
Bus free time between a STOP
and START condition
f
SCL
≤ 100kHz 4.7 – μs
f
SCL
> 100kHz 1.3 – μs
Note:
1. In ATmega32A, this parameter is characterized and not 100% tested.
2. Required only for f
SCL
> 100kHz.
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency
5. This requirement applies to all ATmega32A Two-wire Serial Interface operation. Other devices
connected to the Two-wire Serial Bus need only obey the general f
SCL
requirement.
Figure 30-3. Two-wire Serial Bus Timing
t
SU;S TA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;S TO
t
BUF
SCL
SDA
t
r
30.6. SPI Timing Characteristics
See figures below for details.
Table 30-7. SPI Timing Parameters
Description Mode Min Typ Max
1 SCK period Master See Table 22-5
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • t
SCK
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4 • tck
11 SCK high/low
(1)
Slave 2 • tck
12 Rise/Fall time Slave 1.6 µs
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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