Datasheet

11.6.4. EECR – The EEPROM Control Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Name: EECR
Offset: 0x1C
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x3C
Bit 7 6 5 4 3 2 1 0
EERIE EEMWE EEWE EERE
Access
R/W R/W R/W R/W
Reset 0 0 x 0
Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to
zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is
cleared.
Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When
EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected
address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by
software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for
an EEPROM write procedure.
Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data
are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The
EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write
takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3
and 4 is not essential):
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must
check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only
relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is
never being updated by the CPU, step 2 can be omitted. See Boot Loader Support – Read-While-Write
Self-Programming for details about boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master
Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM
access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It
is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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