Datasheet

Figure 29-10. Serial Programming and Verify
(1)
VCC
GND
XTAL1
SCK
MIS O
MOSI
RESET
PB5
PB6
PB7
+2.7 - 5.5V
AVCC
+2.7 - 5.5V
(2)
Note:
1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. V
CC
- 0.3 < AV
CC
< V
CC
+ 0.3, however, AV
CC
should always be within 2.7 - 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation
(in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip
Erase operation turns the content of every memory location in both the Program and EEPROM arrays
into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the
Serial Clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
≥ 12MHz
High: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
≥ 12MHz
29.9.1. Serial Programming Algorithm
When writing serial data to the ATmega32A, data is clocked on the rising edge of SCK.
When reading data from the ATmega32A, data is clocked on the falling edge of SCK. Please refer to the
figure, Figure 29-11 in SPI Serial Programming Characteristics section for timing details.
To program and verify the ATmega32A in the serial programming mode, the following sequence is
recommended (See Serial Programming Instruction set in Table 29-16 Serial Programming Waveforms:
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some systems, the
programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be
given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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