Datasheet

28.9.1. SPMCR – Store Program Memory Control Register
The Store Program Memory Control and Status Register contains the control bits needed to control the
Boot Loader operations.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Name: SPMCR
Offset: 0x37
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x57
Bit 7 6 5 4 3 2 1 0
SPMIE RWWSB RWWSRE BLBSET PGWRT PGERS SPMEN
Access
R/W R R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready
interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the
SPMCR Register is cleared.
Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (page erase or page write) operation to the RWW section is initiated, the
RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be
accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming
operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation
is initiated.
Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for
reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must
wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to
one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW
section. The RWW section cannot be re-enabled while the Flash is busy with a Page Erase or a Page
Write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load
operation will abort and the data loaded will be lost.
Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles
sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are
ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM
instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR Register
(SPMCR.BLBSET and SPMCR.SPMEN), will read either the Lock bits or the Fuse bits (depending on Z0
in the Z-pointer) into the destination register.
Atmel ATmega32A [DATASHEET]
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