Datasheet

Bit 7 6 5 4 3 2 1 0
Rd – – – – – – LB2 LB1
BLB01
BLB02
BLB11
BLB12
–
– LB2
LB1
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock
Bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in
SPMCR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are
set in the SPMCR, the value of the Fuse Low bits (FLB) will be loaded in the destination register as
shown below. Refer to table Fuse Low Byte in section Fuse Bits for a detailed description and mapping of
the fuse low bits.
Bit 7 6 5 4 3 2 1 0
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0
Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM instruction is
executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the
Fuse High bits (FHB) will be loaded in the destination register as shown below. Refer to table Fuse High
Byte in section Fuse Bits for detailed description and mapping of the fuse high bits.
Bit 7 6 5 4 3 2 1 0
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
Fuse and Lock bits that are programmed read as '0'. Fuse and Lock bits that are unprogrammed, will read
as '1'.
28.8.10. Preventing Flash Corruption
During periods of low V
CC
, the Flash program can be corrupted because the supply voltage is too low for
the CPU and the Flash to operate properly. These issues are the same as for board level systems using
the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular
write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can
execute instructions incorrectly, if the supply voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to
prevent any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be
done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the
detection level. If not, an external low V
CC
reset protection circuit can be used. If a reset occurs
while a write operation is in progress, the write operation will be completed provided that the power
supply voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low V
CC
. This will prevent the
CPU from attempting to decode and execute instructions, effectively protecting the SPMCR
Register and thus the Flash from unintentional writes.
28.8.11. Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. The following table shows the typical
programming time for Flash accesses from the CPU.
Table 28-5. SPM Programming Time
(1)
Symbol Min. Programming Time Max. Programming Time
Flash write (Page Erase, Page Write, and write Lock bits
by SPM)
3.7ms 4.5ms
Note: 1. Minimum and maximum programming time is per individual operation.
Atmel ATmega32A [DATASHEET]
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