Datasheet

27.16.2. MCUCSR – MCU Control and Status Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
The MCU Control and Status Register contains control bits for general MCU functions, and provides
information on which reset source caused an MCU Reset.
Name: MCUCSR
Offset: 0x34
Reset: 0x20
Property: When addressing I/O Registers as data space the offset address is 0x54
Bit 7 6 5 4 3 2 1 0
JTD JTRF
Access
R/W R/W
Reset 0
Bit 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is one,
the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface,
a timed sequence must be followed when changing this bit: The application software must write this bit to
the desired value twice within four cycles to change its value.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to one. The
reason for this is to avoid static current at the TDO pin in the JTAG interface.
Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a Reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG
instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
Atmel ATmega32A [DATASHEET]
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