Datasheet

Figure 11-3. On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Addre s s
Addre s s Valid
T1 T2 T3
Compute Addre s s
Re a d
Write
CPU
Memory Vccess Instruction
Next Ins truction
11.4. EEPROM Data Memory
The Atmel AVR ATmega32A contains 1Kbyte of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at least
100,000 write/erase cycles. The access between the EEPROM and the CPU is described below,
specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control
Register.
Memory Programming contains a detailed description on EEPROM Programming in SPI, JTAG, or
Parallel Programming mode.
Related Links
Memory Programming on page 327
11.4.1. EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in the table "EEPROM Programming Time". A self-timing
function, however, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
CC
is likely to rise or fall slowly on Power-up/down. This causes the device for some period of
time to run at a voltage lower than specified as minimum for the clock frequency used. See Preventing
EEPROM Corruption for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to
the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction
is executed.
Related Links
EECR on page 36
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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