Datasheet

• Shift-DR: The Reset Register is shifted by the TCK input.
27.12.5. BYPASS; 0xF
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
• Capture-DR: Loads a logic “0” into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
27.13. Boundary-scan Chain
The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O
pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip
connections.
27.13.1. Scanning the Digital Port Pins
The first figure below shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The
cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a bi-
directional pin cell that combines the three signals, Output Control – OCxn, Output Data – ODxn, and
Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are not used in the
following description
The Boundary-scan logic is not included in the figures in the Data Sheet. Figure 27-6 shows a simple
digital Port Pin as described in the section I/O Ports. The Boundary-scan details from the first figure below
replaces the dashed box in Figure 27-6.
When no alternate port function is present, the Input Data – ID corresponds to the PINxn Register value
(but ID has no synchronizer), Output Data corresponds to the PORT Register, Output Control
corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – corresponds to logic
expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 27-6 to make the scan
chain read the actual pin value. For Analog function, there is a direct connection from the external pin to
the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog
circuitry.
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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