Datasheet

27.12. Boundry-scan Specific JTAG Instructions
The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG
instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not
implemented, but all outputs with tri-state capability can be set in high-impedant state by using the
AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this data sheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes
which data register is selected as path between TDI and TDO for each instruction.
27.12.1. EXTEST; 0x0
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing circuitry
external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data
are all accessible in the scan chain. For Analog circuits having off-chip connections, the interface
between the analog and the digital logic is in the scan chain. The contents of the latched outputs of the
Boundary-scan chain is driven out as soon as the JTAG IR-register is loaded with the EXTEST
instruction.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to output pins.
27.12.2. IDCODE; 0x1
Optional JTAG instruction selecting the 32-bit ID Register as Data Register. The ID Register consists of a
version number, a device number and the manufacturer code chosen by JEDEC. This is the default
instruction after power-up.
The active states are:
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
27.12.3. SAMPLE_PRELOAD; 0x2
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output
pins without affecting the system operation. However, the output latches are not connected to the pins.
The Boundary-scan Chain is selected as Data Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However, the
output latches are not connected to the pins.
27.12.4. AVR_RESET; 0xC
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the
JTAG Reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is
selected as Data Register. Note that the Reset will be active as long as there is a logic 'one' in the Reset
Chain. The output from this chain is not latched.
The active states are:
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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