Datasheet

held low during input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the
instruction is shifted in when this state is left by setting TMS high. While the instruction is shifted in
from the TDI pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction
selects a particular Data Register as path between TDI and TDO and controls the circuitry
surrounding the selected Data Register.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto
the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and
Exit2-IR states are only used for navigating the state machine.
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data
Register – Shift-DR state. While in this state, upload the selected Data Register (selected by the
present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of
TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits
except the MSB. The MSB of the data is shifted in when this state is left by setting TMS high. While
the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in
the Capture-DR state is shifted out on the TDO pin.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register
has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-
DR, and Exit2-DR states are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG
instruction and using Data Registers, and some JTAG instructions may select certain functions to be
performed in the Run- Test/Idle, making it unsuitable as an Idle state.
Note: 1. Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for 5 TCK clock periods.
For detailed information on the JTAG specification, refer to the literature listed in Bibliography.
27.5. Using the Boundary-scan Chain
A complete description of the Boundary-scan capabilities are given in the section IEEE 1149.1 (JTAG)
Boundary-scan.
27.6. Using the On-chip Debug System
As shown in Figure 27-1, the hardware support for On-chip Debugging consists mainly of:
• A scan chain on the interface between the internal AVR CPU and the internal peripheral units
• Break point unit
• Communication interface between the CPU and JTAG system
All read or modify/write operations needed for implementing the Debugger are done by applying AVR
instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O memory mapped
location which is part of the communication interface between the CPU and the JTAG system.
The Break point Unit implements Break on Change of Program Flow, Single Step Break, two Program
Memory Break points, and two combined break points. Together, the four break points can be configured
as either:
• 4 Single Program Memory break points
• 3 Single Program Memory break points + 1 single Data Memory break point
• 2 Single Program Memory break points + 2 single Data Memory break points
Atmel ATmega32A [DATASHEET]
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