Datasheet

Figure 27-2. TAP Controller State Diagram
Tes t-Logic-Re s e t
Run-Test/Idle
Shift-DR
Exit1-DR
Pa use -DR
Exit2-DR
Update -DR
Se le ct-IR S can
Ca pture-IR
Shift-IR
Exit1-IR
Pa use -IR
Exit2-IR
Update -IR
Se le ct-DR S can
Ca pture-DR
0
1
0
1 1 1
0 0
0 0
1 1
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
00
11
27.4. TAP Controller
The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan
circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure
27-2 depend on the signal present on TMS (shown adjacent to each state transition) at the time of the
rising edge at TCK. The initial state after a Power-on Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all Shift Registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
Instruction Register – Shift-IR state. While in this state, shift the 4 bits of the JTAG instructions into
the JTAG instruction register from the TDI input at the rising edge of TCK. The TMS input must be
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