Datasheet

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input
channel selections will not go into effect until ADEN is set. The ADC does not consume power when
ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By
default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the
ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH.
Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs
to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if
ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and
the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL
Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access
to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if
the result is lost.
26.3. Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit
stays high as long as the conversion is in progress and will be cleared by hardware when the conversion
is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish
the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled
by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS bits for a list of the trigger
sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a
conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal
still is set when the conversion completes, a new conversion will not be started. If another positive edge
occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt flag will be
set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A
conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared
in order to trigger a new conversion at the next interrupt event.
Figure 26-2. ADC Auto Trigger Logic
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START
CLK
ADC
.
.
.
.
EDGE
DETECTOR
ADATE
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the
ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling
and updating the ADC Data Register. The first conversion must be started by writing a logical one to the
ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of
whether the ADC Interrupt Flag, ADIF is cleared or not.
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
260