Datasheet

Figure 10-4. SPH and SPL – Stack Pointer High and Low Register
Bit
15
14
13
12
11
10
9
8
0x3E
S P15
S P14
S P13
S P12
S P11
S P10
S P9
S P8
S PH
0x3D
S P7
S P6
S P5
S P4
S P3
S P2
S P1
S P0
S PL
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Related Links
SRAM Data Memory on page 30
10.6. Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The Atmel AVR CPU
is driven by the CPU clock clk
CPU
, directly generated from the selected clock source for the chip. No
internal clock division is used.
The following figure shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to
obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per
clocks, and functions per power-unit.
Figure 10-5. The Parallel Instruction Fetches and Instruction Executions
clk
1s t Instruction Fe tch
1s t Instruction Execute
2nd Ins truction Fe tch
2nd Ins truction Execute
3rd Ins truction Fetch
3rd Ins truction Execute
4th Ins truction Fetch
T1 T2 T3 T4
CPU
The next figure shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 10-6. Single Cycle ALU Operation
Total Exe cution Time
Re gis te r Operands Fetch
ALU Opera tion Execute
Re sult Write Back
T1 T2 T3 T4
clk
CPU
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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