Datasheet

25.3.2. ACSR – Analog Comparator Control and Status Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Name: ACSR
Offset: 0x08
Reset: N/A
Property: When addressing I/O Registers as data space the offset address is 0x28
Bit 7 6 5 4 3 2 1 0
ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0
Access
R/W R/W R R/W R/W R/W R/W R/W
Reset 0 0 a 0 0 0 0 0
Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set
at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle
mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the
ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog
Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator.
Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1
and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in
SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ACI is cleared by writing a logic one to the flag.
Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator
interrupt is activated. When written logic zero, the interrupt is disabled.
Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by
the Analog Comparator. The comparator output is in this case directly connected to the input capture
front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/
Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog
Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1
Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set.
Bits 1:0 – ACISn: Analog Comparator Interrupt Mode Select [n = 1:0]
These bits determine which comparator events that trigger the Analog Comparator interrupt.
Atmel ATmega32A [DATASHEET]
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