Datasheet

1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the
Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read
from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The
Master must keep control of the bus during all these steps, and the steps should be carried out as an
atomical operation. If this principle is violated in a multimaster system, another Master can alter the data
pointer in the EEPROM between steps 2 and 3, and the Master will read the wrong data location. Such a
change in transfer direction is accomplished by transmitting a REPEATED START between the
transmission of the address byte and reception of the data. After a REPEATED START, the Master keeps
ownership of the bus. The following figure shows the flow in this transfer.
Figure 24-19. Combining Several TWI Modes to Access a Serial EEPROM
Master Transmitter Master Receiv er
S = ST AR T Rs = REPEA TED ST AR T P = ST OP
Transmitted from master to sla v e Transmitted from sla v e to master
S SLA+W A ADDRESS A Rs SLA+R A DATA A P
24.7. Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one
or more of them. The TWI standard ensures that such situations are handled in such a way that one of
the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An
example of an arbitration situation is depicted below, where two masters are trying to transmit data to a
Slave Receiver.
Figure 24-20. An Arbitration Example
Device 1
MASTER
TRANSMITTER
Device 2
MASTER
TRANSMITTER
Device 3
SLA VE
RECEIVER
Device n
SD A
SCL
........
R1 R2
V
CC
Several different scenarios may arise during arbitration, as described below:
• Two or more masters are performing identical communication with the same Slave. In this case,
neither the Slave nor any of the masters will know about the bus contention.
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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