Datasheet

23.11.4. UCSRC – USART Control and Status Register C
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
The UCSRC Register shares the same I/O location as the UBRRH Register. See the Accessing UBRRH/
UCSRC Registers section which describes how to access this register.
Name: UCSRC
Offset: 0x20
Reset: 0x06
Property: When addressing I/O Registers as data space the offset address is 0x40
Bit 7 6 5 4 3 2 1 0
URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 0 0 0 0 0 1 0
Bit 7 – URSEL: Register Select
This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when reading
UCSRC. The URSEL must be one when writing the UCSRC.
Bit 6 – UMSEL: Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
Table 23-4. UMSEL Bit Settings
UMSEL Bit Settings Mode
0 Asynchronous Operation
1 Synchronous Operation
Bits 5:4 – UPMn: Parity Mode [n = 1:0]
These bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The Receiver
will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is
detected, the PE Flag in UCSRA will be set.
Table 23-5. UPM Bits Settings
UPM1 UPM0 ParityMode
0 0 Disabled
0 1 Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Bit 3 – USBS: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this
setting.
Atmel ATmega32A [DATASHEET]
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