Datasheet

23.11.2. UCSRA – USART Control and Status Register A
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Name: UCSRA
Offset: 0x0B
Reset: 0x20
Property: When addressing I/O Registers as data space the offset address is 0x2B
Bit 7 6 5 4 3 2 1 0
RXC TXC UDRE FE DOR PE U2X MPCM
Access
R R/W R R R R R/W R/W
Reset 0 0 1 0 0 0 0 0
Bit 7 – RXC: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is
empty (i.e. does not contain any unread data). If the Receiver is disabled, the receive buffer will be
flushed and consequently the RXC bit will become zero. The RXC Flag can be used to generate a
Receive Complete interrupt (see description of the RXCIE bit).
Bit 6 – TXC: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are
no new data currently present in the transmit buffer (UDR). The TXC Flag bit is automatically cleared
when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The
TXC Flag can generate a Transmit Complete interrupt (see description of the TXCIE bit).
Bit 5 – UDRE: USART Data Register Empty
The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the
buffer is empty, and therefore ready to be written. The UDRE Flag can generate a Data Register Empty
interrupt (see description of the UDRIE bit).
UDRE is set after a reset to indicate that the Transmitter is ready.
Bit 4 – FE: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when received (i.e., when the
first stop bit of the next character in the receive buffer is zero). This bit is valid until the receive buffer
(UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero
when writing to UCSRA.
Bit 3 – DOR: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is
full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is
detected. This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to
UCSRA.
Bit 2 – PE: Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the parity
checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read.
Always set this bit to zero when writing to UCSRA.
Atmel ATmega32A [DATASHEET]
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