Datasheet
Table Of Contents
- Introduction
- Features
- Table of Contents
- 1. Description
- 2. Configuration Summary
- 3. Ordering Information
- 4. Block Diagram
- 5. Pin Configurations
- 6. Resources
- 7. Data Retention
- 8. About Code Examples
- 9. Capacitive Touch Sensing
- 10. AVR CPU Core
- 11. AVR Memories
- 12. System Clock and Clock Options
- 13. Power Management and Sleep Modes
- 14. System Control and Reset
- 15. Interrupts
- 16. External Interrupts
- 17. I/O Ports
- 17.1. Overview
- 17.2. Ports as General Digital I/O
- 17.3. Alternate Port Functions
- 17.4. Register Description
- 17.4.1. SFIOR – Special Function IO Register
- 17.4.2. PORTA – Port A Data Register
- 17.4.3. DDRA – Port A Data Direction Register
- 17.4.4. PINA – Port A Input Pins Address
- 17.4.5. PORTB – The Port B Data Register
- 17.4.6. DDRB – The Port B Data Direction Register
- 17.4.7. PINB – The Port B Input Pins Address
- 17.4.8. PORTC – The Port C Data Register
- 17.4.9. DDRC – The Port C Data Direction Register
- 17.4.10. PINC – The Port C Input Pins Address
- 17.4.11. PORTD – The Port D Data Register
- 17.4.12. DDRD – The Port D Data Direction Register
- 17.4.13. PIND – The Port D Input Pins Address
- 18. Timer/Counter0 and Timer/Counter1 Prescalers
- 19. 16-bit Timer/Counter1
- 19.1. Features
- 19.2. Overview
- 19.3. Accessing 16-bit Registers
- 19.4. Timer/Counter Clock Sources
- 19.5. Counter Unit
- 19.6. Input Capture Unit
- 19.7. Output Compare Units
- 19.8. Compare Match Output Unit
- 19.9. Modes of Operation
- 19.10. Timer/Counter Timing Diagrams
- 19.11. Register Description
- 19.11.1. TCCR1A – Timer/Counter1 Control Register A
- 19.11.2. TCCR1B – Timer/Counter1 Control Register B
- 19.11.3. TCNT1L – Timer/Counter1 Low byte
- 19.11.4. TCNT1H – Timer/Counter1 High byte
- 19.11.5. OCR1AL – Output Compare Register 1 A Low byte
- 19.11.6. OCR1AH – Output Compare Register 1 A High byte
- 19.11.7. OCR1BL – Output Compare Register 1 B Low byte
- 19.11.8. OCR1BH – Output Compare Register 1 B High byte
- 19.11.9. ICR1L – Input Capture Register 1 Low byte
- 19.11.10. ICR1H – Input Capture Register 1 High byte
- 19.11.11. TIMSK – Timer/Counter Interrupt Mask Register
- 19.11.12. TIFR – Timer/Counter Interrupt Flag Register
- 20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 20.1. Features
- 20.2. Overview
- 20.3. Timer/Counter Clock Sources
- 20.4. Counter Unit
- 20.5. Output Compare Unit
- 20.6. Compare Match Output Unit
- 20.7. Modes of Operation
- 20.8. Timer/Counter Timing Diagrams
- 20.9. Asynchronous Operation of the Timer/Counter
- 20.10. Timer/Counter Prescaler
- 20.11. Register Description
- 20.11.1. TCCR2 – Timer/Counter Control Register
- 20.11.2. TCNT0 – Timer/Counter Register
- 20.11.3. OCR0 – Output Compare Register
- 20.11.4. ASSR – Asynchronous Status Register
- 20.11.5. TIMSK – Timer/Counter Interrupt Mask Register
- 20.11.6. TIFR – Timer/Counter Interrupt Flag Register
- 20.11.7. SFIOR – Special Function IO Register
- 21. 8-bit Timer/Counter0 with PWM
- 22. SPI – Serial Peripheral Interface
- 23. USART - Universal Synchronous and Asynchronous serial Receiver and Transmitter
- 23.1. Features
- 23.2. Overview
- 23.3. Clock Generation
- 23.4. Frame Formats
- 23.5. USART Initialization
- 23.6. Data Transmission – The USART Transmitter
- 23.7. Data Reception – The USART Receiver
- 23.8. Asynchronous Data Reception
- 23.9. Multi-Processor Communication Mode
- 23.10. Accessing UBRRH/UCSRC Registers
- 23.11. Register Description
- 23.12. Examples of Baud Rate Setting
- 24. TWI - Two-wire Serial Interface
- 25. AC - Analog Comparator
- 26. ADC - Analog to Digital Converter
- 26.1. Features
- 26.2. Overview
- 26.3. Starting a Conversion
- 26.4. Prescaling and Conversion Timing
- 26.5. Changing Channel or Reference Selection
- 26.6. ADC Noise Canceler
- 26.7. ADC Conversion Result
- 26.8. Register Description
- 26.8.1. ADMUX – ADC Multiplexer Selection Register
- 26.8.2. ADCSRA – ADC Control and Status Register A
- 26.8.3. ADCL – ADC Data Register Low (ADLAR=0)
- 26.8.4. ADCH – ADC Data Register High (ADLAR=0)
- 26.8.5. ADCL – ADC Data Register Low (ADLAR=1)
- 26.8.6. ADCH – ADC Data Register High (ADLAR=1)
- 26.8.7. SFIOR – Special Function IO Register
- 27. JTAG Interface and On-chip Debug System
- 27.1. Features
- 27.2. Overview
- 27.3. TAP – Test Access Port
- 27.4. TAP Controller
- 27.5. Using the Boundary-scan Chain
- 27.6. Using the On-chip Debug System
- 27.7. On-chip Debug Specific JTAG Instructions
- 27.8. Using the JTAG Programming Capabilities
- 27.9. Bibliography
- 27.10. IEEE 1149.1 (JTAG) Boundary-scan
- 27.11. Data Registers
- 27.12. Boundry-scan Specific JTAG Instructions
- 27.13. Boundary-scan Chain
- 27.14. ATmega32A Boundary-scan Order
- 27.15. Boundary-scan Description Language Files
- 27.16. Register Description
- 28. BTLDR - Boot Loader Support – Read-While-Write Self-Programming
- 28.1. Features
- 28.2. Overview
- 28.3. Application and Boot Loader Flash Sections
- 28.4. Read-While-Write and No Read-While-Write Flash Sections
- 28.5. Boot Loader Lock Bits
- 28.6. Entering the Boot Loader Program
- 28.7. Addressing the Flash During Self-Programming
- 28.8. Self-Programming the Flash
- 28.8.1. Performing Page Erase by SPM
- 28.8.2. Filling the Temporary Buffer (Page Loading)
- 28.8.3. Performing a Page Write
- 28.8.4. Using the SPM Interrupt
- 28.8.5. Consideration While Updating Boot Loader Section (BLS)
- 28.8.6. Prevent Reading the RWW Section During Self-Programming
- 28.8.7. Setting the Boot Loader Lock Bits by SPM
- 28.8.8. EEPROM Write Prevents Writing to SPMCR
- 28.8.9. Reading the Fuse and Lock Bits from Software
- 28.8.10. Preventing Flash Corruption
- 28.8.11. Programming Time for Flash when Using SPM
- 28.8.12. Simple Assembly Code Example for a Boot Loader
- 28.8.13. ATmega32A Boot Loader Parameters
- 28.9. Register Description
- 29. Memory Programming
- 29.1. Program and Data Memory Lock Bits
- 29.2. Fuse Bits
- 29.3. Signature Bytes
- 29.4. Signature Bytes
- 29.5. Calibration Byte
- 29.6. Parallel Programming Parameters, Pin Mapping, and Commands
- 29.7. Parallel Programming
- 29.7.1. Enter Programming Mode
- 29.7.2. Considerations for Efficient Programming
- 29.7.3. Chip Erase
- 29.7.4. Programming the Flash
- 29.7.5. Programming the EEPROM
- 29.7.6. Reading the Flash
- 29.7.7. Reading the EEPROM
- 29.7.8. Programming the Fuse Low Bits
- 29.7.9. Programming the Fuse High Bits
- 29.7.10. Programming the Lock Bits
- 29.7.11. Reading the Fuse and Lock Bits
- 29.7.12. Reading the Signature Bytes
- 29.7.13. Reading the Calibration Byte
- 29.7.14. Parallel Programming Characteristics
- 29.8. Serial Downloading
- 29.9. Serial Programming Pin Mapping
- 29.10. Programming Via the JTAG Interface
- 29.10.1. Programming Specific JTAG Instructions
- 29.10.2. AVR_RESET (0xC)
- 29.10.3. PROG_ENABLE (0x4)
- 29.10.4. PROG_COMMANDS (0x5)
- 29.10.5. PROG_PAGELOAD (0x6)
- 29.10.6. PROG_PAGEREAD (0x7)
- 29.10.7. Data Registers
- 29.10.8. Reset Register
- 29.10.9. Programming Enable Register
- 29.10.10. Programming Command Register
- 29.10.11. Virtual Flash Page Load Register
- 29.10.12. Virtual Flash Page Read Register
- 29.10.13. Programming Algorithm
- 29.10.14. Entering Programming Mode
- 29.10.15. Leaving Programming Mode
- 29.10.16. Performing Chip Erase
- 29.10.17. Programming the Flash
- 29.10.18. Reading the Flash
- 29.10.19. Programming the EEPROM
- 29.10.20. Reading the EEPROM
- 29.10.21. Programming the Fuses
- 29.10.22. Programming the Lock Bits
- 29.10.23. Reading the Fuses and Lock Bits
- 29.10.24. Reading the Signature Bytes
- 29.10.25. Reading the Calibration Byte
- 30. Electrical Characteristics
- 31. Typical Characteristics
- 31.1. Active Supply Current
- 31.2. Idle Supply Current
- 31.3. Power-down Supply Current
- 31.4. Power-save Supply current
- 31.5. Standby Supply Current
- 31.6. Pin Pull-up
- 31.7. Pin Driver Strength
- 31.8. Pin Thresholds and Hysteresis
- 31.9. BOD Thresholds and Analog Comparator Offset
- 31.10. Internal Oscillator Speed
- 31.11. Current Consumption of Peripheral Units
- 31.12. Current Consumption in Reset and Reset Pulsewidth
- 32. Register Summary
- 33. Instruction Set Summary
- 34. Packaging Information
- 35. Errata
- 36. Datasheet Revision History

The following code example shows a simple USART receive function based on polling of the Receive
Complete (RXC) Flag. When using frames with less than eight bits the most significant bits of the data
read from the UDR will be masked to zero. The USART has to be initialized before the function can be
used.
Assembly Code Example
(1)
USART_Receive:
; Wait for data to be received
sbis UCSRA, RXC
rjmp USART_Receive
; Get and return received data from buffer
in r16, UDR
ret
C Code Example
(1)
unsigned char USART_Receive( void )
{
/* Wait for data to be received */
while ( !(UCSRA & (1<<RXC)) )
;
/* Get and return received data from buffer */
return UDR;
}
Note: 1. See About Code Examples.
The function simply waits for data to be present in the receive buffer by checking the
RXC Flag, before reading the buffer and returning the value.
Related Links
About Code Examples on page 19
23.7.2. Receiving Frames with 9 Data Bits
If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before
reading the low bits from the UDR. This rule applies to the FE, DOR and PE Status Flags as well. Read
status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the
receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO,
will change.
The following code example shows a simple USART receive function that handles both 9-bit characters
and the status bits.
Assembly Code Example
(1)
USART_Receive:
; Wait for data to be received
sbis r16, RXC
rjmp USART_Receive
; Get status and 9th bit, then data from buffer
in r18, UCSRA
in r17, UCSRB
in r16, UDR
; If error, return -1
andi r18,(1<<FE)|(1<<DOR)|(1<<PE)
breq USART_ReceiveNoError
ldi r17, HIGH(-1)
ldi r16, LOW(-1)
USART_ReceiveNoError:
; Filter the 9th bit, then return
lsr r17
andi r17, 0x01
ret
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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