Datasheet

23.6.3. Transmitter Flags and Interrupts
The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and
Transmit Complete (TXC). Both flags can be used for generating interrupts.
The Data Register Empty (UDRE) Flag indicates whether the transmit buffer is ready to receive new data.
This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be
transmitted that has not yet been moved into the Shift Register. For compatibility with future devices,
always write this bit to zero when writing the UCSRA Register.
When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data
Register Empty Interrupt will be executed as long as UDRE is set (provided that global interrupts are
enabled). UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the Data
Register empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the
Data Register empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has
been shifted out and there are no new data currently present in the transmit buffer. The TXC Flag bit is
automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one
to its bit location. The TXC Flag is useful in half-duplex communication interfaces (like the RS485
standard), where a transmitting application must enter Receive mode and free the communication bus
immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit
Complete Interrupt will be executed when the TXC Flag becomes set (provided that global interrupts are
enabled). When the transmit complete interrupt is used, the interrupt handling routine does not have to
clear the TXC Flag, this is done automatically when the interrupt is executed.
23.6.4. Parity Generator
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPM1
= 1), the Transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the
frame that is sent.
23.6.5. Disabling the Transmitter
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and
pending transmissions are completed (i.e., when the Transmit Shift Register and Transmit Buffer Register
do not contain data to be transmitted). When disabled, the Transmitter will no longer override the TxD pin.
23.7. Data Reception – The USART Receiver
The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to
one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART
and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format
must be set up once before any serial reception can be done. If synchronous operation is used, the clock
on the XCK pin will be used as transfer clock.
23.7.1. Receiving Frames with 5 to 8 Data Bits
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be
sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until the first stop bit of
a frame is received. A second stop bit will be ignored by the Receiver. When the first stop bit is received
(i.e., a complete serial frame is present in the Receive Shift Register), the contents of the Shift Register
will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O
location.
Atmel ATmega32A [DATASHEET]
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