Datasheet

At the very start of period 2 in the timing diagram OCn has a transition from high to low even though there
is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are
two cases that give a transition without a Compare Match:
• OCR0 changes its value from MAX, like in the timing diagram above. When the OCR0 value is MAX the
OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around
BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR0, and for that reason misses the
Compare Match and hence the OCn change that would have happened on the way up.
21.8. Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as a clock
enable signal in the following figures. The figures include information on when interrupt flags are set. The
first figure below contains timing data for basic Timer/Counter operation. It shows the count sequence
close to the MAX value in all modes other than phase correct PWM mode.
Figure 21-8. Timer/Counter Timing Diagram, no Prescaling
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
The next figure shows the same timing data, but with the prescaler enabled.
Figure 21-9. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
The next figure shows the setting of OCF0 in all modes except CTC mode.
Atmel ATmega32A [DATASHEET]
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