Datasheet

21.7. Modes of Operation
The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined
by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode
(COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform
Generation mode bits do. The COM01:0 bits control whether the PWM output generated should be
inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM01:0 bits control whether
the output should be set, cleared, or toggled at a Compare Match (see Compare Match Output Unit).
For detailed timing information refer to Timer/Counter Timing Diagrams.
21.7.1. Normal Mode
The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction
is always up (incrementing), and no counter clear is performed. The counter simply overruns when it
passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal
operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0
becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer
resolution can be increased by software. There are no special cases to consider in the Normal mode, a
new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of
the CPU time.
21.7.2. Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches
the OCR0. The OCR0 defines the top value for the counter, hence also its resolution. This mode allows
greater control of the Compare Match output frequency. It also simplifies the operation of counting
external events.
The timing diagram for the CTC mode is shown in the figure below. The counter value (TCNT0) increases
until a Compare Match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared.
Figure 21-5. CTC Mode, Timing Diagram
TCNTn
OCn
(Toggle)
OCn Inte rrupt Flag Se t
1 4
Pe riod
2 3
(COMn1:0 = 1)
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0
Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low
prescaler value must be done with care since the CTC mode does not have the double buffering feature.
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
167