Datasheet

Figure 21-2. Counter Unit Block Diagram
DATA BUS
TCNTn Control Logic
count
TOVn
(Int. Req.)
TOPBOTTOM
direction
clear
(From Prescaler)
Tn
Clock Select
Edge
Detector
Signal description (internal signals):
count Increment or decrement TCNT0 by 1.
direction Selects between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clk
T0
Timer/Counter clock.
TOP Signalizes that TCNT0 has reached maximum value.
BOTTOM Signalizes that TCNT0 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each
timer clock (clk
T0
). clk
T0
can be generated from an external or internal clock source, selected by the clock
select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the
TCNT0 value can be accessed by the CPU, regardless of whether clk
T0
is present or not. A CPU write
overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/
Counter Control Register (TCCR0). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare Output OC0. For more details about
advanced counting sequences and waveform generation, see Modes of Operation.
The Timer/Counter Overflow (TOV0) Flag is set according to the mode of operation selected by the
WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
21.5. Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0).
Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the Output Compare
Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1 and global interrupt flag in SREG is set),
the Output Compare Flag generates an Output Compare interrupt. The OCF0 Flag is automatically
cleared when the interrupt is executed. Alternatively, the OCF0 Flag can be cleared by software by writing
a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output
according to operating mode set by the WGM01:0 bits and Compare Output mode (COM01:0) bits. The
max and bottom signals are used by the waveform generator for handling the special cases of the
extreme values in some modes of operation (see Modes of Operation).
The following figure shows a block diagram of the Output Compare unit.
Atmel ATmega32A [DATASHEET]
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